soc/interconnect/wishbone: allow setting adr_width (default to 30)
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@ -13,7 +13,7 @@ from litex.soc.interconnect import csr
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_layout = [
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("adr", 30, DIR_M_TO_S),
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("adr", "adr_width", DIR_M_TO_S),
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("dat_w", "data_width", DIR_M_TO_S),
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("dat_r", "data_width", DIR_S_TO_M),
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("sel", "sel_width", DIR_M_TO_S),
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@ -28,8 +28,9 @@ _layout = [
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class Interface(Record):
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def __init__(self, data_width=32):
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def __init__(self, data_width=32, adr_width=30):
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Record.__init__(self, set_layout_parameters(_layout,
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adr_width=adr_width,
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data_width=data_width,
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sel_width=data_width//8))
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