remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)

make.py

@@ -6,7 +6,7 @@ from mibuild.tools import write_to_file
 from migen.util.misc import autotype
 from migen.fhdl import simplify
 
-from misoclib.gensoc import cpuif
+from misoclib.soc import cpuif
 from misoclib.cpu import CPU
 from misoclib.mem.sdram.phy import initsequence
 

misoclib/com/liteeth/example_designs/targets/base.py

@@ -55,7 +55,7 @@ class _CRG(Module):
 			AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
 		]
 
-class GenSoC(Module):
+class SoC(Module):
 	csr_base = 0x00000000
 	csr_data_width = 32
 	csr_map = {
@@ -109,17 +109,17 @@ class GenSoC(Module):
 		for name, memory, mapaddr, mmap in self.csrbankarray.srams:
 			self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
 
-class BaseSoC(GenSoC, AutoCSR):
+class BaseSoC(SoC, AutoCSR):
 	default_platform = "kc705"
 	csr_map = {
 		"phy":		11,
 		"core":		12
 	}
-	csr_map.update(GenSoC.csr_map)
+	csr_map.update(SoC.csr_map)
 	def __init__(self, platform, clk_freq=166*1000000,
 			mac_address=0x10e2d5000000,
 			ip_address="192.168.1.40"):
-		GenSoC.__init__(self, platform, clk_freq)
+		SoC.__init__(self, platform, clk_freq)
 		self.submodules.crg = _CRG(platform)
 
 		# wishbone SRAM (to test Wishbone over UART and Etherbone)

misoclib/mem/litesata/example_designs/targets/bist.py

@@ -55,7 +55,7 @@ class _CRG(Module):
 			AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
 		]
 
-class GenSoC(Module):
+class SoC(Module):
 	csr_base = 0x00000000
 	csr_data_width = 32
 	csr_map = {
@@ -130,15 +130,15 @@ class BISTLeds(Module):
 		self.comb += platform.request("user_led", 2).eq(sata_phy.crg.ready)
 		self.comb += platform.request("user_led", 3).eq(sata_phy.ctrl.ready)
 
-class BISTSoC(GenSoC, AutoCSR):
+class BISTSoC(SoC, AutoCSR):
 	default_platform = "kc705"
 	csr_map = {
 		"sata":		10,
 	}
-	csr_map.update(GenSoC.csr_map)
+	csr_map.update(SoC.csr_map)
 	def __init__(self, platform):
 		clk_freq = 166*1000000
-		GenSoC.__init__(self, platform, clk_freq)
+		SoC.__init__(self, platform, clk_freq)
 		self.submodules.crg = _CRG(platform)
 
 		# SATA PHY/Core/Frontend

misoclib/soc/__init__.py

@@ -17,7 +17,7 @@ from misoclib.mem.sdram import memtest
 def mem_decoder(address, start=26, end=29):
 	return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
 
-class GenSoC(Module):
+class SoC(Module):
 	csr_map = {
 		"crg":					0, # user
 		"uart":					1, # provided by default (optional)
@@ -160,7 +160,7 @@ class GenSoC(Module):
 		if isinstance(self.cpu_or_bridge, CPU):
 			for mem in ["rom", "sram"]:
 				if mem not in registered_mems:
-					raise FinalizeError("CPU needs a {} to be registered with GenSoC.register_mem()".format(mem))
+					raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem))
 
 		# Wishbone
 		self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
@@ -192,7 +192,7 @@ class GenSoC(Module):
 	def do_exit(self, vns):
 		pass
 
-class SDRAMSoC(GenSoC):
+class SDRAMSoC(SoC):
 	csr_map = {
 		"dfii":					6,
 		"lasmicon":				7,
@@ -200,14 +200,14 @@ class SDRAMSoC(GenSoC):
 		"memtest_w":			9,
 		"memtest_r":			10
 	}
-	csr_map.update(GenSoC.csr_map)
+	csr_map.update(SoC.csr_map)
 
 	def __init__(self, platform, clk_freq,
 			ramcon_type="lasmicon",
 			with_l2=True, l2_size=8192,
 			with_memtest=False,
 			**kwargs):
-		GenSoC.__init__(self, platform, clk_freq, **kwargs)
+		SoC.__init__(self, platform, clk_freq, **kwargs)
 		self.ramcon_type = ramcon_type
 
 		self.with_l2 = with_l2
@@ -268,4 +268,4 @@ class SDRAMSoC(GenSoC):
 	def do_finalize(self):
 		if not self._sdram_phy_registered:
 			raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
-		GenSoC.do_finalize(self)
+		SoC.do_finalize(self)

misoclib/tools/litescope/example_designs/targets/simple.py

@@ -27,7 +27,7 @@ class _CRG(Module):
 			self.cd_sys.rst.eq(~rst_n)
 		]
 
-class GenSoC(Module):
+class SoC(Module):
 	csr_base = 0x00000000
 	csr_data_width = 32
 	csr_map = {
@@ -71,16 +71,16 @@ class GenSoC(Module):
 		for name, memory, mapaddr, mmap in self.csrbankarray.srams:
 			self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
 
-class LiteScopeSoC(GenSoC, AutoCSR):
+class LiteScopeSoC(SoC, AutoCSR):
 	default_platform = "de0nano"
 	csr_map = {
 		"io":	10,
 		"la":	11
 	}
-	csr_map.update(GenSoC.csr_map)
+	csr_map.update(SoC.csr_map)
 	def __init__(self, platform):
 		clk_freq = 50*1000000
-		GenSoC.__init__(self, platform, clk_freq)
+		SoC.__init__(self, platform, clk_freq)
 		self.submodules.crg = _CRG(platform.request("clk50"))
 
 		self.submodules.io = LiteScopeIO(8)

targets/de0nano.py

@@ -5,7 +5,7 @@ from misoclib.cpu.peripherals import gpio
 from misoclib.mem import sdram
 from misoclib.mem.sdram.phy import gensdrphy
 from misoclib.com import uart
-from misoclib.gensoc import SDRAMSoC
+from misoclib.soc import SDRAMSoC
 
 class _PLL(Module):
 	def __init__(self, period_in, name, phase_shift, operation_mode):

targets/kc705.py

@@ -4,7 +4,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from misoclib.mem import sdram
 from misoclib.mem.sdram.phy import k7ddrphy
 from misoclib.mem.flash import spiflash
-from misoclib.gensoc import SDRAMSoC, mem_decoder
+from misoclib.soc import SDRAMSoC, mem_decoder
 
 from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
 from misoclib.com.liteeth.mac import LiteEthMAC

targets/mlabs_video.py

@@ -10,7 +10,7 @@ from misoclib.mem.sdram.phy import s6ddrphy
 from misoclib.mem.flash import norflash16
 from misoclib.cpu.peripherals import gpio
 from misoclib.video import framebuffer
-from misoclib.gensoc import SDRAMSoC, mem_decoder
+from misoclib.soc import SDRAMSoC, mem_decoder
 
 from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
 from misoclib.com.liteeth.mac import LiteEthMAC

targets/pipistrello.py

@@ -6,7 +6,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from misoclib.mem import sdram
 from misoclib.mem.sdram.phy import gensdrphy
 from misoclib.mem.flash import SpiFlash
-from misoclib.gensoc import SDRAMSoC
+from misoclib.soc import SDRAMSoC
 
 class _CRG(Module):
 	def __init__(self, platform, clk_freq):

targets/ppro.py

@@ -6,7 +6,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from misoclib.mem import sdram
 from misoclib.mem.sdram.phy import gensdrphy
 from misoclib.mem.flash import spiflash
-from misoclib.gensoc import SDRAMSoC
+from misoclib.soc import SDRAMSoC
 
 class _CRG(Module):
 	def __init__(self, platform, clk_freq):

targets/simple.py

@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 from migen.bus import wishbone
 
-from misoclib.gensoc import GenSoC, mem_decoder
+from misoclib.soc import SoC, mem_decoder
 
 class _CRG(Module):
 	def __init__(self, clk_in):
@@ -17,9 +17,9 @@ class _CRG(Module):
 			self.cd_sys.rst.eq(~rst_n)
 		]
 
-class SimpleSoC(GenSoC):
+class SimpleSoC(SoC):
 	def __init__(self, platform, **kwargs):
-		GenSoC.__init__(self, platform,
+		SoC.__init__(self, platform,
 			clk_freq=int((1/(platform.default_clk_period))*1000000000),
 			with_rom=True,
 			with_sdram=True, sdram_size=16*1024,