gen/fhdl: add Display for debug in simulation

litex/gen/fhdl/structure.py

@@ -718,3 +718,8 @@ class _Fragment:
         self.specials |= other.specials
         self.clock_domains += other.clock_domains
         return self
+
+class Display:
+    def __init__(self, s, *args):
+        self.s = s
+        self.args = args

litex/gen/fhdl/verilog.py

@@ -118,6 +118,15 @@ def _printexpr(ns, node):
 def _printnode(ns, at, level, node):
     if node is None:
         return ""
+    elif isinstance(node, Display):
+        s = "\"" + node.s + "\\r\""
+        for arg in node.args:
+            s += ", "
+            if isinstance(arg, Signal):
+                s += ns.get_name(arg)
+            else:
+                s += str(arg)
+        return "\t"*level + "$display(" + s + ");\n"
     elif isinstance(node, _Assign):
         if at == _AT_BLOCKING:
             assignment = " = "