Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

command: fix TX path with random acknowledge

Browse source
This commit is contained in:
Florent Kermarrec 2014-12-14 21:03:14 +01:00
parent ddc99febb5
commit 6a783ad291
3 changed files with 10 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
lib/sata/command/__init__.py
View file

@ -55,7 +55,7 @@ class SATACommandTX(Module):
) )
) )
fsm.act("SEND_WRITE_DMA_CMD", fsm.act("SEND_WRITE_DMA_CMD",
transport.sink.stb.eq(1), transport.sink.stb.eq(sink.stb),
transport.sink.sop.eq(1), transport.sink.sop.eq(1),
transport.sink.eop.eq(1), transport.sink.eop.eq(1),
transport.sink.type.eq(fis_types["REG_H2D"]), transport.sink.type.eq(fis_types["REG_H2D"]),

6
lib/sata/test/command_tb.py
View file

@ -106,7 +106,7 @@ class TB(Module):
def __init__(self): def __init__(self):
self.submodules.hdd = HDD( self.submodules.hdd = HDD(
phy_debug=False, phy_debug=False,
link_random_level=25, link_debug=False, link_random_level=50, link_debug=False,
transport_debug=False, transport_loopback=False, transport_debug=False, transport_loopback=False,
command_debug=False, command_debug=False,
hdd_debug=True) hdd_debug=True)
@ -115,10 +115,10 @@ class TB(Module):
self.submodules.command = SATACommand(self.transport) self.submodules.command = SATACommand(self.transport)
self.submodules.streamer = CommandStreamer() self.submodules.streamer = CommandStreamer()
streamer_ack_randomizer = AckRandomizer(command_tx_description(32), level=0) streamer_ack_randomizer = AckRandomizer(command_tx_description(32), level=50)
self.submodules += streamer_ack_randomizer self.submodules += streamer_ack_randomizer
self.submodules.logger = CommandLogger() self.submodules.logger = CommandLogger()
logger_ack_randomizer = AckRandomizer(command_rx_description(32), level=25) logger_ack_randomizer = AckRandomizer(command_rx_description(32), level=50)
self.submodules += logger_ack_randomizer self.submodules += logger_ack_randomizer
self.comb += [ self.comb += [
Record.connect(self.streamer.source, streamer_ack_randomizer.sink), Record.connect(self.streamer.source, streamer_ack_randomizer.sink),

12
lib/sata/transport/__init__.py
View file

@ -54,13 +54,13 @@ class SATATransportTX(Module):
sink.ack.eq(1) sink.ack.eq(1)
) )
).Else( ).Else(
sink.ack.eq(1) sink.ack.eq(sink.stb)
) )
) )
fsm.act("SEND_REG_H2D_CMD", fsm.act("SEND_REG_H2D_CMD",
_encode_cmd(sink, fis_reg_h2d_layout, encoded_cmd), _encode_cmd(sink, fis_reg_h2d_layout, encoded_cmd),
cmd_len.eq(fis_reg_h2d_cmd_len-1), cmd_len.eq(fis_reg_h2d_cmd_len-1),
cmd_send.eq(sink.stb), cmd_send.eq(1),
If(cmd_done, If(cmd_done,
sink.ack.eq(1), sink.ack.eq(1),
NextState("IDLE") NextState("IDLE")
@ -70,7 +70,7 @@ class SATATransportTX(Module):
_encode_cmd(sink, fis_data_layout, encoded_cmd), _encode_cmd(sink, fis_data_layout, encoded_cmd),
cmd_len.eq(fis_data_cmd_len-1), cmd_len.eq(fis_data_cmd_len-1),
cmd_with_data.eq(1), cmd_with_data.eq(1),
cmd_send.eq(sink.stb), cmd_send.eq(1),
If(cmd_done, If(cmd_done,
NextState("SEND_DATA") NextState("SEND_DATA")
) )
@ -89,12 +89,12 @@ class SATATransportTX(Module):
self.comb += \ self.comb += \
If(cmd_send, If(cmd_send,
link.sink.stb.eq(1), link.sink.stb.eq(sink.stb),
link.sink.sop.eq(cnt==0), link.sink.sop.eq(cnt==0),
link.sink.eop.eq((cnt==cmd_len) & ~cmd_with_data), link.sink.eop.eq((cnt==cmd_len) & ~cmd_with_data),
Case(cnt, cmd_cases), Case(cnt, cmd_cases),
inc_cnt.eq(link.sink.ack), inc_cnt.eq(sink.stb & link.sink.ack),
cmd_done.eq((cnt==cmd_len) & link.sink.ack) cmd_done.eq((cnt==cmd_len) & link.sink.stb & link.sink.ack)
).Elif(data_send, ).Elif(data_send,
link.sink.stb.eq(sink.stb), link.sink.stb.eq(sink.stb),
link.sink.sop.eq(0), link.sink.sop.eq(0),