trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5

Passing '-nowidelut' to yosys' synth_ecp5 command improves area utilization
to the point where a (linux variant) rocket-chip based design will fit on a
versa_ecp5 board. Usually '-nowidelut' incurs a timing penalty, but that is
then mitigated by using DSP inference (enabled by default from yosys commit
8474c5b3).

Off by default, this flag can be enabled by adding '--yosys-nowidelut=True'
to the litex/boards/targets/versa_ecp5.py command line.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

litex/boards/targets/versa_ecp5.py

@@ -11,6 +11,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.boards.platforms import versa_ecp5
 
+from litex.build.lattice.trellis import yosys_args, yosys_argdict
+
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
@@ -133,6 +135,7 @@ def main():
         help='gateware toolchain to use, diamond (default) or  trellis')
     builder_args(parser)
     soc_sdram_args(parser)
+    yosys_args(parser)
     parser.add_argument("--sys-clk-freq", default=75e6,
                         help="system clock frequency (default=75MHz)")
     parser.add_argument("--with-ethernet", action="store_true",
@@ -142,7 +145,7 @@ def main():
     cls = EthernetSoC if args.with_ethernet else BaseSoC
     soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
-    builder.build()
+    builder.build(**yosys_argdict(args))
 
 if __name__ == "__main__":
     main()

litex/build/lattice/trellis.py

@@ -138,7 +138,7 @@ class LatticeTrellisToolchain:
         self.yosys_template = [
             "{read_files}",
             "attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
-            "synth_ecp5 -abc9 -json {build_name}.json -top {build_name}",
+            "synth_ecp5 -abc9 {nwl} -json {build_name}.json -top {build_name}",
         ]
 
         self.build_template = [
@@ -150,7 +150,7 @@ class LatticeTrellisToolchain:
         self.freq_constraints = dict()
 
     def build(self, platform, fragment, build_dir="build", build_name="top",
-              toolchain_path=None, run=True, **kwargs):
+              toolchain_path=None, run=True, nowidelut=False, **kwargs):
         if toolchain_path is None:
             toolchain_path = "/usr/share/trellis/"
         os.makedirs(build_dir, exist_ok=True)
@@ -175,6 +175,7 @@ class LatticeTrellisToolchain:
         # generate yosys script
         yosys_script_file = build_name + ".ys"
         yosys_script_contents = "\n".join(_.format(build_name=build_name,
+                                                   nwl="-nowidelut" if nowidelut else "",
                                                    read_files=yosys_import_sources(platform))
                                           for _ in self.yosys_template)
         tools.write_to_file(yosys_script_file, yosys_script_contents)
@@ -202,3 +203,12 @@ class LatticeTrellisToolchain:
     # constraints.
     def add_period_constraint(self, platform, clk, period):
         platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
+
+def yosys_args(parser):
+    parser.add_argument("--yosys-nowidelut", action="store_true",
+                        help="pass '-nowidelut' to yosys synth_ecp5")
+
+def yosys_argdict(args):
+    return {
+        "nowidelut": args.yosys_nowidelut
+    }