examples/basic/psync: demonstrate the new features
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from migen.fhdl.structure import *
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from migen.fhdl.specials import SynthesisDirective
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from migen.fhdl import verilog
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from migen.genlib.cdc import *
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# convert pulse into level change
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i = Signal()
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level = Signal()
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isync = [If(i, level.eq(~level))]
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class XilinxMultiRegImpl(MultiRegImpl):
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def get_fragment(self):
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disable_srl = set(SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
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for r in self.regs)
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return MultiRegImpl.get_fragment(self) + Fragment(specials=disable_srl)
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# synchronize level to oclk domain
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slevel = [Signal() for i in range(3)]
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osync = [
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slevel[0].eq(level),
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slevel[1].eq(slevel[0]),
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slevel[2].eq(slevel[1])
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]
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class XilinxMultiReg(Special):
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@staticmethod
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def lower(dr):
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return XilinxMultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n)
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# disable shift register extraction
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disable_srl = {
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SynthesisDirective("attribute shreg_extract of {signal} is no", signal=slevel[0]),
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SynthesisDirective("attribute shreg_extract of {signal} is no", signal=slevel[1])
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}
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# regenerate pulse
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o = Signal()
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comb = [o.eq(slevel[1] ^ slevel[2])]
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f = Fragment(comb, {"i": isync, "o": osync}, specials=disable_srl)
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v = verilog.convert(f, {i, o})
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ps = PulseSynchronizer("from", "to")
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f = ps.get_fragment()
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v = verilog.convert(f, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
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print(v)
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