soc/cores/clock/efinix: don't hardcore create_clock (fix warning because clock is created after set_false_path), explicit clock name (fix warning when signal is absorbed)
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@ -96,11 +96,13 @@ class EFINIXPLL(LiteXModule):
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assert self.nclkouts < self.nclkouts_max
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assert self.nclkouts < self.nclkouts_max
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clk_out_name = f"{self.name}_clkout{self.nclkouts}" if name == "" else name
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clk_out_name = f"{self.name}_clkout{self.nclkouts}" if name == "" else name
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self.platform.toolchain.additional_sdc_commands.append(f"create_clock -period {1e9/freq} {clk_out_name}")
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if cd is not None:
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if cd is not None:
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self.platform.add_extension([(clk_out_name, 0, Pins(1))])
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self.platform.add_extension([(clk_out_name, 0, Pins(1))])
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self.comb += cd.clk.eq(self.platform.request(clk_out_name))
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clk_name = f"{cd.name}_clk"
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clk_out = self.platform.request(clk_out_name)
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self.comb += cd.clk.eq(clk_out)
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self.platform.add_period_constraint(clk=clk_out, period=1e9/freq, name=clk_name)
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if with_reset:
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if with_reset:
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self.specials += AsyncResetSynchronizer(cd, ~self.locked)
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self.specials += AsyncResetSynchronizer(cd, ~self.locked)
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self.platform.toolchain.excluded_ios.append(clk_out_name)
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self.platform.toolchain.excluded_ios.append(clk_out_name)
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