Merge pull request #1179 from Technosystem-Labs/vexriscv_hw_breakpoints
Added Vexriscv hardware breakpoint variants for Mini and Lite.
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6b3eda16f2
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@ -24,8 +24,10 @@ from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
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CPU_VARIANTS = {
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CPU_VARIANTS = {
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"minimal": "VexRiscv_Min",
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"minimal": "VexRiscv_Min",
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"minimal+debug": "VexRiscv_MinDebug",
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"minimal+debug": "VexRiscv_MinDebug",
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"minimal+debug+hwbp": "VexRiscv_MinDebugHwBP",
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"lite": "VexRiscv_Lite",
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"lite": "VexRiscv_Lite",
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"lite+debug": "VexRiscv_LiteDebug",
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"lite+debug": "VexRiscv_LiteDebug",
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"lite+debug+hwbp": "VexRiscv_LiteDebugHwBP",
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"standard": "VexRiscv",
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"standard": "VexRiscv",
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"standard+debug": "VexRiscv_Debug",
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"standard+debug": "VexRiscv_Debug",
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"imac": "VexRiscv_IMAC",
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"imac": "VexRiscv_IMAC",
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