bus/wishbone: configurable data width
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@ -6,22 +6,23 @@ from migen.bus.transactions import *
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from migen.sim.generic import Proxy
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_layout = [
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("adr", 30, DIR_M_TO_S),
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("dat_w", 32, DIR_M_TO_S),
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("dat_r", 32, DIR_S_TO_M),
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("sel", 4, DIR_M_TO_S),
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("cyc", 1, DIR_M_TO_S),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M),
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("we", 1, DIR_M_TO_S),
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("cti", 3, DIR_M_TO_S),
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("bte", 2, DIR_M_TO_S),
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("err", 1, DIR_S_TO_M)
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("adr", 30, DIR_M_TO_S),
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("dat_w", "data_width", DIR_M_TO_S),
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("dat_r", "data_width", DIR_S_TO_M),
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("sel", "sel_width", DIR_M_TO_S),
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("cyc", 1, DIR_M_TO_S),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M),
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("we", 1, DIR_M_TO_S),
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("cti", 3, DIR_M_TO_S),
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("bte", 2, DIR_M_TO_S),
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("err", 1, DIR_S_TO_M)
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]
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class Interface(Record):
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def __init__(self):
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Record.__init__(self, _layout)
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def __init__(self, data_width=32):
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Record.__init__(self, _layout, data_width=data_width,
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sel_width=data_width//8)
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class InterconnectPointToPoint(Module):
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def __init__(self, master, slave):
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