bus/wishbone: configurable data width
This commit is contained in:
parent
14ed5c1acc
commit
6ba0d4bd0d
|
@ -7,9 +7,9 @@ from migen.sim.generic import Proxy
|
|||
|
||||
_layout = [
|
||||
("adr", 30, DIR_M_TO_S),
|
||||
("dat_w", 32, DIR_M_TO_S),
|
||||
("dat_r", 32, DIR_S_TO_M),
|
||||
("sel", 4, DIR_M_TO_S),
|
||||
("dat_w", "data_width", DIR_M_TO_S),
|
||||
("dat_r", "data_width", DIR_S_TO_M),
|
||||
("sel", "sel_width", DIR_M_TO_S),
|
||||
("cyc", 1, DIR_M_TO_S),
|
||||
("stb", 1, DIR_M_TO_S),
|
||||
("ack", 1, DIR_S_TO_M),
|
||||
|
@ -20,8 +20,9 @@ _layout = [
|
|||
]
|
||||
|
||||
class Interface(Record):
|
||||
def __init__(self):
|
||||
Record.__init__(self, _layout)
|
||||
def __init__(self, data_width=32):
|
||||
Record.__init__(self, _layout, data_width=data_width,
|
||||
sel_width=data_width//8)
|
||||
|
||||
class InterconnectPointToPoint(Module):
|
||||
def __init__(self, master, slave):
|
||||
|
|
Loading…
Reference in New Issue