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cores/spi: simplify.

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This commit is contained in:
Florent Kermarrec 2020-04-22 12:20:23 +02:00
parent fc434af949
commit 6bb22dfe6b
1 changed files with 13 additions and 12 deletions
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17
litex/soc/cores/spi.py
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@ -98,30 +98,31 @@ class SPIMaster(Module, AutoCSR):
# Master Out Slave In (MOSI) generation (generated on spi_clk falling edge) --------------- # Master Out Slave In (MOSI) generation (generated on spi_clk falling edge) ---------------
mosi_data = Signal(data_width) mosi_data = Signal(data_width)
self.sync += \ self.sync += [
If(self.start, If(self.start,
mosi_data.eq(self.mosi) mosi_data.eq(self.mosi)
).Elif(clk_rise & shift, ).Elif(clk_rise & shift,
mosi_data.eq(Cat(Signal(), mosi_data[:-1])) mosi_data.eq(Cat(Signal(), mosi_data))
).Elif(clk_fall, ).Elif(clk_fall,
pads.mosi.eq(mosi_data[-1]) pads.mosi.eq(mosi_data[-1])
) )
]
# Master In Slave Out (MISO) capture (captured on spi_clk rising edge) -------------------- # Master In Slave Out (MISO) capture (captured on spi_clk rising edge) --------------------
miso = Signal() miso = Signal()
miso_data = self.miso miso_data = self.miso
self.sync += \ self.sync += [
If(shift, If(clk_rise & shift,
If(clk_rise,
If(self.loopback, If(self.loopback,
miso.eq(pads.mosi) miso.eq(pads.mosi)
).Else( ).Else(
miso.eq(pads.miso) miso.eq(pads.miso)
) )
).Elif(clk_fall, ),
miso_data.eq(Cat(miso, miso_data[:-1])) If(clk_fall & shift,
) miso_data.eq(Cat(miso, miso_data))
) )
]
def add_csr(self): def add_csr(self):
self._control = CSRStorage(fields=[ self._control = CSRStorage(fields=[