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graycounter: expose binary output
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parent
0f9df2d732
commit
6c08cd67aa
2 changed files with 8 additions and 8 deletions
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@ -11,8 +11,8 @@ class TB(Module):
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self.prng = Random(7345)
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def do_simulation(self, s):
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print("{0:0{1}b} CE={2}".format(s.rd(self.gc.q),
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self.width, s.rd(self.gc.ce)))
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print("{0:0{1}b} CE={2} bin={3}".format(s.rd(self.gc.q),
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self.width, s.rd(self.gc.ce), s.rd(self.gc.q_binary)))
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s.wr(self.gc.ce, self.prng.getrandbits(1))
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sim = Simulator(TB())
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@ -78,20 +78,20 @@ class GrayCounter(Module):
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self.ce = Signal()
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self.q = Signal(width)
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self.q_next = Signal(width)
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self.q_binary = Signal(width)
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self.q_next_binary = Signal(width)
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###
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q_binary = Signal(width)
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q_next_binary = Signal(width)
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self.comb += [
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If(self.ce,
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q_next_binary.eq(q_binary + 1)
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self.q_next_binary.eq(self.q_binary + 1)
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).Else(
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q_next_binary.eq(q_binary)
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self.q_next_binary.eq(self.q_binary)
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),
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self.q_next.eq(q_next_binary ^ q_next_binary[1:])
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self.q_next.eq(self.q_next_binary ^ self.q_next_binary[1:])
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]
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self.sync += [
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q_binary.eq(q_next_binary),
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self.q_binary.eq(self.q_next_binary),
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self.q.eq(self.q_next)
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]
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