build/xilinx/vivado: Add XilinxVivadoCommands for pre_synthesis/placement/routing_commands with add method to automatically resolve LiteX signals'names.
This makes it similar to add_platform_command and add more flexibility to constraint the design.
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@ -102,6 +102,22 @@ def _run_script(script):
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# XilinxVivadoToolchain ----------------------------------------------------------------------------
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class XilinxVivadoCommands(list):
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def add(self, command, **signals):
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self.append((command, signals))
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def resolve(self, vns):
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named_commands = []
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for command in self:
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if isinstance(command, str):
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named_commands.append(command)
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else:
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template, args = command
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name_dict = dict((k, vns.get_name(sig)) for k, sig in args.items())
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named_commands.append(template.format(**name_dict))
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return named_commands
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class XilinxVivadoToolchain:
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attr_translate = {
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"keep": ("dont_touch", "true"),
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@ -116,9 +132,9 @@ class XilinxVivadoToolchain:
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def __init__(self):
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self.bitstream_commands = []
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self.additional_commands = []
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self.pre_synthesis_commands = []
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self.pre_placement_commands = []
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self.pre_routing_commands = []
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self.pre_synthesis_commands = XilinxVivadoCommands()
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self.pre_placement_commands = XilinxVivadoCommands()
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self.pre_routing_commands = XilinxVivadoCommands()
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self.incremental_implementation = False
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self.vivado_synth_directive = "default"
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self.opt_directive = "default"
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@ -129,7 +145,7 @@ class XilinxVivadoToolchain:
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self.clocks = dict()
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self.false_paths = set()
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def _build_tcl(self, platform, build_name, synth_mode, enable_xpm):
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def _build_tcl(self, platform, build_name, synth_mode, enable_xpm, vns):
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assert synth_mode in ["vivado", "yosys"]
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tcl = []
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@ -191,7 +207,7 @@ class XilinxVivadoToolchain:
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# Add pre-synthesis commands
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tcl.append("\n# Add pre-synthesis commands\n")
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tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
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tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands.resolve(vns))
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# Synthesis
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if synth_mode == "vivado":
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@ -223,7 +239,7 @@ class XilinxVivadoToolchain:
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# Add pre-placement commands
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tcl.append("\n# Add pre-placement commands\n")
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tcl.extend(c.format(build_name=build_name) for c in self.pre_placement_commands)
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tcl.extend(c.format(build_name=build_name) for c in self.pre_placement_commands.resolve(vns))
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# Placement
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tcl.append("\n# Placement\n")
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@ -239,7 +255,7 @@ class XilinxVivadoToolchain:
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# Add pre-routing commands
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tcl.append("\n# Add pre-routing commands\n")
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tcl.extend(c.format(build_name=build_name) for c in self.pre_routing_commands)
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tcl.extend(c.format(build_name=build_name) for c in self.pre_routing_commands.resolve(vns))
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# Routing
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tcl.append("\n# Routing\n")
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@ -341,7 +357,8 @@ class XilinxVivadoToolchain:
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platform = platform,
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build_name = build_name,
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synth_mode = synth_mode,
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enable_xpm = enable_xpm
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enable_xpm = enable_xpm,
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vns = v_output.ns,
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)
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# Generate design constraints (.xdc)
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