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cpu/gowin_emcu: Switch to LiteX's UART (Using integrated UART is not really useful for now and make things less flexible, ie no UARTBone/Crossover possibilities).

This commit is contained in:
Florent Kermarrec 2024-01-04 11:29:12 +01:00
parent 6a6837062a
commit 6c6c238309
4 changed files with 2 additions and 91 deletions
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5
litex/soc/cores/cpu/gowin_emcu/core.py
View File

@ -47,7 +47,6 @@ class GowinEMCU(CPU):
def gcc_flags(self):
flags = f" -march=armv7-m -mthumb"
flags += f" -D__CortexM3__"
flags += f" -DUART_POLLING"
return flags
def __init__(self, platform, variant="standard"):
@ -64,8 +63,8 @@ class GowinEMCU(CPU):
self.cpu_params = dict(
# Clk/Rst.
i_FCLK = ClockSignal("sys"),
i_PORESETN = ~ (ResetSignal("sys") | self.reset),
i_SYSRESETN = ~ (ResetSignal("sys") | self.reset),
i_PORESETN = ~(ResetSignal("sys") | self.reset),
i_SYSRESETN = ~(ResetSignal("sys") | self.reset),
i_MTXREMAP = Signal(4, reset=0b1111),
o_MTXHRESETN = bus_reset_n,

3
litex/soc/cores/cpu/gowin_emcu/crt0.c
View File

@ -19,9 +19,6 @@ void _start(void) {
for (uint32_t *x = &_fbss; x < &_ebss; x ++)
*x = 0;
UART0->ctrl = 0b11; // set rx and tx enable bits
UART0->baud_div = CONFIG_CLOCK_FREQUENCY / 115200; // FIXME
__asm__("bl main");
while(1);
}

33
litex/soc/cores/cpu/gowin_emcu/irq.h
View File

@ -1,37 +1,4 @@
#ifndef __IRQ_H
#define __IRQ_H
#ifdef __cplusplus
extern "C" {
#endif
static inline unsigned int irq_getie(void)
{
return 0; /* FIXME */
}
static inline void irq_setie(unsigned int ie)
{
/* FIXME */
}
static inline unsigned int irq_getmask(void)
{
return 0; /* FIXME */
}
static inline void irq_setmask(unsigned int mask)
{
/* FIXME */
}
static inline unsigned int irq_pending(void)
{
return 0; /* FIXME */
}
#ifdef __cplusplus
}
#endif
#endif /* __IRQ_H */

52
litex/soc/cores/cpu/gowin_emcu/system.h
View File

@ -12,58 +12,6 @@ void flush_l2_cache(void);
void busy_wait(unsigned int ms);
void busy_wait_us(unsigned int us);
#include <stdint.h>
// FIXME
#define CSR_UART_BASE
struct EMCU_UART
{
volatile uint32_t data;
volatile uint32_t state;
volatile uint32_t ctrl;
volatile uint32_t int_ctrl;
volatile uint32_t baud_div;
};
#define PERIPHERALS_BASE 0x40000000
#define UART0 ((struct EMCU_UART *) (PERIPHERALS_BASE + 0x4000))
static inline char uart_txfull_read(void);
static inline char uart_rxempty_read(void);
static inline void uart_ev_enable_write(char c);
static inline void uart_rxtx_write(char c);
static inline char uart_rxtx_read(void);
static inline void uart_ev_pending_write(char);
static inline char uart_ev_pending_read(void);
static inline char uart_txfull_read(void) {
return UART0->state & 0b01;
}
static inline char uart_rxempty_read(void) {
return !(UART0->state & 0b10);
}
static inline void uart_ev_enable_write(char c) {
// FIXME
}
static inline void uart_rxtx_write(char c) {
UART0->data = (uint32_t) c;
}
static inline char uart_rxtx_read(void)
{
return (char)(UART0->data);
}
static inline void uart_ev_pending_write(char x) {}
static inline char uart_ev_pending_read(void) {
return 0;
}
#ifdef __cplusplus
}
#endif