soc_core: fix uart stub

2020-01-13 16:56:31 +01:00 · 2020-01-13 16:56:31 +01:00 · 6c9f418d26
parent 63cd23c9c3
commit 6c9f418d26
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@ -242,7 +242,7 @@ class SoCCore(Module):
            if uart_name in ["stub", "stream"]:
                self.submodules.uart = uart.UART()
                if uart_name == "stub":
-                    self.comb += uart.sink.ready.eq(1)
+                    self.comb += self.uart.sink.ready.eq(1)
            elif uart_name == "crossover":
                self.submodules.uart = uart.UARTCrossover()
            else: