{Dep,p}acketizer: handle transactions of a single bus word
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@ -238,7 +238,7 @@ class Packetizer(Module):
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self.sync += If(source.ready, sink_d.eq(sink))
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fsm.act("UNALIGNED-DATA-COPY",
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source.valid.eq(sink.valid | sink_d.last),
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source.last.eq(sink_d.last),
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source.last.eq(sink.last | sink_d.last),
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If(fsm_from_idle,
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source.data[:max(header_leftover*8, 1)].eq(sr[min(header_offset_multiplier*data_width, len(sr)-1):])
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).Else(
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@ -246,7 +246,7 @@ class Packetizer(Module):
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),
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source.data[header_leftover*8:].eq(sink.data),
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If(source.valid & source.ready,
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sink.ready.eq(~source.last),
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sink.ready.eq(~source.last | sink.last),
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NextValue(fsm_from_idle, 0),
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If(source.last,
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NextState("IDLE")
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@ -414,13 +414,13 @@ class Depacketizer(Module):
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self.sync += If(sink.valid & sink.ready, sink_d.eq(sink))
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fsm.act("UNALIGNED-DATA-COPY",
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source.valid.eq(sink.valid | sink_d.last),
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source.last.eq(sink.last | sink_d.last),
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sink.ready.eq(source.ready),
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source.last.eq(sink_d.last),
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sink.ready.eq(source.ready & ~source.last),
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source.data.eq(sink_d.data[header_leftover*8:]),
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source.data[min((bytes_per_clk-header_leftover)*8, data_width-1):].eq(sink.data),
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If(fsm_from_idle,
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source.valid.eq(sink_d.last),
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sink.ready.eq(1),
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sink.ready.eq(~sink_d.last),
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If(sink.valid,
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NextValue(fsm_from_idle, 0),
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sr_shift_leftover.eq(1),
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