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framebuffer: reset VTG

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This commit is contained in:
Sebastien Bourdeauducq 2013-11-15 11:25:07 +01:00
parent a5d9f72901
commit 6cb18f5ce3
2 changed files with 33 additions and 22 deletions
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2
misoclib/framebuffer/__init__.py
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@ -32,6 +32,7 @@ class Framebuffer(Module, AutoCSR):
self.comb += [ self.comb += [
self.fi.trigger.eq(self._enable.storage), self.fi.trigger.eq(self._enable.storage),
self.dma.generator.trigger.eq(self._enable.storage), self.dma.generator.trigger.eq(self._enable.storage),
vtg.enable.eq(self._enable.storage)
] ]
class Blender(PipelinedActor, AutoCSR): class Blender(PipelinedActor, AutoCSR):
@ -104,6 +105,7 @@ class MixFramebuffer(Module, AutoCSR):
setattr(self, "dma"+str(n), dma) setattr(self, "dma"+str(n), dma)
vtg = VTG() vtg = VTG()
self.comb += vtg.enable.eq(self._enable.storage)
g.add_connection(self.fi, vtg, sink_ep="timing") g.add_connection(self.fi, vtg, sink_ep="timing")
g.add_connection(self.blender, vtg, sink_ep="pixels") g.add_connection(self.blender, vtg, sink_ep="pixels")
g.add_connection(vtg, self.driver) g.add_connection(vtg, self.driver)

11
misoclib/framebuffer/format.py
View file

@ -50,6 +50,7 @@ class FrameInitiator(spi.SingleGenerator):
class VTG(Module): class VTG(Module):
def __init__(self): def __init__(self):
self.enable = Signal()
self.timing = Sink([ self.timing = Sink([
("hres", _hbits), ("hres", _hbits),
("hsync_start", _hbits), ("hsync_start", _hbits),
@ -63,6 +64,8 @@ class VTG(Module):
self.phy = Source(phy_layout) self.phy = Source(phy_layout)
self.busy = Signal() self.busy = Signal()
###
hactive = Signal() hactive = Signal()
vactive = Signal() vactive = Signal()
active = Signal() active = Signal()
@ -81,12 +84,13 @@ class VTG(Module):
), ),
generate_en.eq(self.timing.stb & (~active | self.pixels.stb)), generate_en.eq(self.timing.stb & (~active | self.pixels.stb)),
self.pixels.ack.eq(self.phy.ack & active), self.pixels.ack.eq(~self.enable | (self.phy.ack & active)),
self.phy.stb.eq(generate_en), self.phy.stb.eq(generate_en),
self.busy.eq(generate_en) self.busy.eq(generate_en)
] ]
tp = self.timing.payload tp = self.timing.payload
self.sync += [ self.sync += [
If(self.enable,
self.timing.ack.eq(0), self.timing.ack.eq(0),
If(generate_en & self.phy.ack, If(generate_en & self.phy.ack,
hcounter.eq(hcounter + 1), hcounter.eq(hcounter + 1),
@ -110,4 +114,9 @@ class VTG(Module):
If(vcounter == tp.vsync_start, self.phy.payload.vsync.eq(1)), If(vcounter == tp.vsync_start, self.phy.payload.vsync.eq(1)),
If(vcounter == tp.vsync_end, self.phy.payload.vsync.eq(0)) If(vcounter == tp.vsync_end, self.phy.payload.vsync.eq(0))
) )
).Else(
self.timing.ack.eq(1),
hcounter.eq(0),
vcounter.eq(0)
)
] ]