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soc/interconnect/axi: connect axi.ar/aw when selecting write or read

This commit is contained in:
Florent Kermarrec 2019-05-02 09:58:55 +02:00
parent 6affc56a09
commit 6cf1ff091c
1 changed files with 2 additions and 4 deletions
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6
litex/soc/interconnect/axi.py
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@ -139,13 +139,14 @@ class AXI2Wishbone(Module):
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
If(axi.ar.valid, If(axi.ar.valid,
axi.ar.connect(ax_burst),
NextState("DO-READ") NextState("DO-READ")
).Elif(axi.aw.valid, ).Elif(axi.aw.valid,
axi.aw.connect(ax_burst),
NextState("DO-WRITE") NextState("DO-WRITE")
) )
) )
fsm.act("DO-READ", fsm.act("DO-READ",
axi.ar.connect(ax_burst),
wishbone.stb.eq(1), wishbone.stb.eq(1),
wishbone.cyc.eq(1), wishbone.cyc.eq(1),
wishbone.adr.eq(_addr[wishbone_adr_shift:]), wishbone.adr.eq(_addr[wishbone_adr_shift:]),
@ -155,7 +156,6 @@ class AXI2Wishbone(Module):
) )
) )
fsm.act("SEND-READ-RESPONSE", fsm.act("SEND-READ-RESPONSE",
axi.ar.connect(ax_burst),
axi.r.valid.eq(1), axi.r.valid.eq(1),
axi.r.resp.eq(RESP_OKAY), axi.r.resp.eq(RESP_OKAY),
axi.r.id.eq(ax_beat.id), axi.r.id.eq(ax_beat.id),
@ -171,7 +171,6 @@ class AXI2Wishbone(Module):
) )
) )
fsm.act("DO-WRITE", fsm.act("DO-WRITE",
axi.aw.connect(ax_burst),
wishbone.stb.eq(axi.w.valid), wishbone.stb.eq(axi.w.valid),
wishbone.cyc.eq(axi.w.valid), wishbone.cyc.eq(axi.w.valid),
wishbone.we.eq(1), wishbone.we.eq(1),
@ -188,7 +187,6 @@ class AXI2Wishbone(Module):
) )
) )
fsm.act("SEND-WRITE-RESPONSE", fsm.act("SEND-WRITE-RESPONSE",
axi.aw.connect(ax_burst),
axi.b.valid.eq(1), axi.b.valid.eq(1),
axi.b.resp.eq(RESP_OKAY), axi.b.resp.eq(RESP_OKAY),
axi.b.id.eq(ax_beat.id), axi.b.id.eq(ax_beat.id),