Merge pull request #2046 from enjoy-digital/hyperbus_2x
HyperRAM: Add 2:1 ratio support in addition of 4:1 ratio.
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commit
6d0ae25d65
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@ -44,10 +44,27 @@ class HyperRAM(LiteXModule):
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pads (Record) : Platform pads of HyperRAM.
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bus (wishbone.Interface) : Wishbone Interface.
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"""
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def __init__(self, pads, latency=6, latency_mode="variable", sys_clk_freq=10e6, with_csr=True):
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def __init__(self, pads, latency=6, latency_mode="variable", sys_clk_freq=10e6, clk_ratio="4:1", with_csr=True):
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self.pads = pads
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self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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# # #
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# Parameters.
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# -----------
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dw = len(pads.dq) if not hasattr(pads.dq, "oe") else len(pads.dq.o)
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assert dw in [8, 16]
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assert latency_mode in ["fixed", "variable"]
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assert clk_ratio in [
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"4:1", # HyperRAM Clk = Sys Clk/4.
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"2:1", # HyperRAM Clk = Sys Clk/2.
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]
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self.cd_io = cd_io = {
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"4:1": "sys",
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"2:1": "sys2x"
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}[clk_ratio]
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self.sync_io = sync_io = getattr(self.sync, cd_io)
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# Config/Reg Interface.
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# ---------------------
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self.conf_rst = Signal()
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@ -63,14 +80,6 @@ class HyperRAM(LiteXModule):
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if with_csr:
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self.add_csr(default_latency=latency)
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# # #
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# Parameters.
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# -----------
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dw = len(pads.dq) if not hasattr(pads.dq, "oe") else len(pads.dq.o)
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assert dw in [8, 16]
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assert latency_mode in ["fixed", "variable"]
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# Internal Signals.
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# -----------------
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clk = Signal()
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@ -100,7 +109,7 @@ class HyperRAM(LiteXModule):
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rwds.o.eq( rwds_o),
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rwds.oe.eq(rwds_oe),
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]
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self.sync += [
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self.sync_io += [
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# DQ.
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dq_i.eq(dq.i),
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@ -112,15 +121,15 @@ class HyperRAM(LiteXModule):
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# Rst.
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if hasattr(pads, "rst_n"):
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self.sync += pads.rst_n.eq(1 & ~self.conf_rst)
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self.sync_io += pads.rst_n.eq(1 & ~self.conf_rst)
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# CSn.
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pads.cs_n.reset = 2**len(pads.cs_n) - 1
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self.sync += pads.cs_n[0].eq(~cs) # Only supporting 1 CS.
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self.sync_io += pads.cs_n[0].eq(~cs) # Only supporting 1 CS.
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# Clk.
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pads_clk = Signal()
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self.sync += pads_clk.eq(clk)
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self.sync_io += pads_clk.eq(clk)
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if hasattr(pads, "clk"):
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# Single Ended Clk.
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self.comb += pads.clk.eq(pads_clk)
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@ -133,14 +142,11 @@ class HyperRAM(LiteXModule):
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# Burst Timer ------------------------------------------------------------------------------
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self.burst_timer = burst_timer = WaitTimer(sys_clk_freq * self.tCSM)
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# Clock Generation (sys_clk/4) -------------------------------------------------------------
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self.sync += [
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# Clk Generation ---------------------------------------------------------------------------
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self.sync_io += [
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clk_phase.eq(0b00),
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If(cs,
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# Increment Clk Phase on CS.
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clk_phase.eq(clk_phase + 1)
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).Else(
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# Else set Clk Phase to default value.
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clk_phase.eq(0b00)
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)
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]
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cases = {
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@ -149,7 +155,10 @@ class HyperRAM(LiteXModule):
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0b10 : clk.eq(cs), # 180°
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0b11 : clk.eq(0), # 270° / Clr Clk.
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}
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self.comb += Case(clk_phase, cases)
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if clk_ratio in ["4:1"]:
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self.comb += Case(clk_phase, cases)
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if clk_ratio in ["2:1"]:
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self.sync_io += Case(clk_phase, cases)
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# Data Shift-In Register -------------------------------------------------------------------
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self.comb += [
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@ -162,7 +171,10 @@ class HyperRAM(LiteXModule):
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sr_next[dw:].eq(sr),
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)
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]
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self.sync += If(clk_phase[0] == 0, sr.eq(sr_next)) # Shift on 0°/180° (and sampled on 90°/270°).
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if clk_ratio in ["4:1"]:
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self.sync += If(clk_phase[0] == 0, sr.eq(sr_next))
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if clk_ratio in ["2:1"]:
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self.sync += sr.eq(sr_next)
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# Data Shift-Out Register ------------------------------------------------------------------
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self.comb += bus.dat_r.eq(sr_next)
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@ -250,7 +262,7 @@ class HyperRAM(LiteXModule):
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# Send Command on DQ.
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ca_oe.eq(1),
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dq_oe.eq(1),
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# Wait for 6*2 cycles...
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# Wait for 6*2 cycles.
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If(cycles == (6*2 - 1),
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If(reg_write_req,
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NextValue(sr, Cat(Signal(40), self.reg_write_data[8:])),
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@ -266,7 +278,7 @@ class HyperRAM(LiteXModule):
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# Send Reg on DQ.
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ca_oe.eq(1),
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dq_oe.eq(1),
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# Wait for 2 cycles...
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# Wait for 2 cycles.
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If(cycles == (2 - 1),
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NextValue(sr, Cat(Signal(40), self.reg_write_data[:8])),
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NextState("REG-WRITE-1")
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@ -276,7 +288,7 @@ class HyperRAM(LiteXModule):
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# Send Reg on DQ.
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ca_oe.eq(1),
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dq_oe.eq(1),
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# Wait for 2 cycles...
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# Wait for 2 cycles.
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If(cycles == (2 - 1),
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reg_ep.ready.eq(1),
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NextValue(self.reg_write_done, 1),
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@ -308,7 +320,7 @@ class HyperRAM(LiteXModule):
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rwds_oe.eq(1),
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*[rwds_o[dw//8-1-i].eq(~bus_sel[4-1-n*dw//8-i]) for i in range(dw//8)],
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),
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# Wait for 2 cycles (since HyperRAM's Clk = sys_clk/4).
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# Wait for 2 cycles.
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If(cycles == (2 - 1),
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# Set next default state (with rollover for bursts).
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NextState(f"READ-WRITE-DATA{(n + 1)%states}"),
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@ -347,8 +359,16 @@ class HyperRAM(LiteXModule):
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# FSM Cycles -------------------------------------------------------------------------------
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fsm.finalize()
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self.sync += cycles.eq(cycles + 1)
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self.sync += If(fsm.next_state != fsm.state, cycles.eq(0))
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cycles_rst = {
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"4:1" : 0,
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"2:1" : 1,
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}[clk_ratio]
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cycles_inc = {
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"4:1" : 1,
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"2:1" : 2,
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}[clk_ratio]
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self.sync += cycles.eq(cycles + cycles_inc)
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self.sync += If(fsm.next_state != fsm.state, cycles.eq(cycles_rst))
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def add_tristate(self, pad, register=False):
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class TristatePads:
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@ -363,7 +383,7 @@ class HyperRAM(LiteXModule):
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o = t.o[n],
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oe = t.oe,
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i = t.i[n],
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clk = ClockSignal("sys"),
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clk = ClockSignal(cd_io),
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)
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else:
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self.specials += Tristate(pad,
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@ -388,9 +408,19 @@ class HyperRAM(LiteXModule):
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CSRField("latency_mode", offset=0, size=1, values=[
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("``0b0``", "Fixed Latency."),
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("``0b1``", "Variable Latency."),
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])
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]),
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CSRField("clk_ratio", offset=1, size=4, values=[
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("``4``", "HyperRAM Clk = Sys Clk/4."),
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("``2``", "HyperRAM Clk = Sys Clk/2."),
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]),
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])
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self.comb += self.status.fields.latency_mode.eq(self.stat_latency_mode)
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self.comb += [
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self.status.fields.latency_mode.eq(self.stat_latency_mode),
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self.status.fields.clk_ratio.eq({
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"sys" : 4,
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"sys2x": 2,
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}[self.cd_io]),
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]
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# Reg Interface.
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# --------------
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@ -57,12 +57,15 @@ static uint16_t hyperram_get_chip_latency_setting(uint32_t clk_freq) {
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static void hyperram_configure_latency(void) {
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uint16_t config_reg_0 = 0x8f2f;
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uint8_t core_clk_ratio;
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uint16_t core_latency_setting;
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uint16_t chip_latency_setting;
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/* Compute Latency settings */
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core_latency_setting = hyperram_get_core_latency_setting(CONFIG_CLOCK_FREQUENCY/4);
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chip_latency_setting = hyperram_get_chip_latency_setting(CONFIG_CLOCK_FREQUENCY/4);
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core_clk_ratio = (hyperram_status_read() >> CSR_HYPERRAM_STATUS_CLK_RATIO_OFFSET & 0xf);
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printf("HyperRAM Clk Ratio %d:1.\n", core_clk_ratio);
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core_latency_setting = hyperram_get_core_latency_setting(CONFIG_CLOCK_FREQUENCY/core_clk_ratio);
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chip_latency_setting = hyperram_get_chip_latency_setting(CONFIG_CLOCK_FREQUENCY/core_clk_ratio);
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/* Write Latency to HyperRAM Core */
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printf("HyperRAM Core Latency: %d CK (X1).\n", core_latency_setting);
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@ -58,6 +58,39 @@ class TestHyperBus(unittest.TestCase):
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dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_write_latency_5_2x_sys2x(self):
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def fpga_gen(dut):
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yield from dut.bus.write(0x1234, 0xdeadbeef, sel=0b1001)
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yield
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def hyperram_gen(dut):
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clk = "____--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "--________________________________________________________-------"
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dq_oe = "___------------____________________________________--------______"
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dq_o = "0002000048d0000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "___________________________________________________--------______"
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rwds_o = "_____________________________________________________----________"
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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#if (yield dut.pads.dq.oe):
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# self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed", clk_ratio="2:1")
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generators = {
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"sys" : fpga_gen(dut),
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"sys2x" : hyperram_gen(dut),
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}
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clocks = {
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"sys" : 4,
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"sys2x" : 2,
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}
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run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
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def test_hyperram_write_latency_6_2x(self):
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def fpga_gen(dut):
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yield from dut.bus.write(0x1234, 0xdeadbeef, sel=0b1001)
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