fhdl/FullMemoryWE: fix clocking

2015-09-29 13:12:27 +08:00 · 2015-09-29 13:12:27 +08:00 · 6d2d70d879
parent b4c5ffc1ba
commit 6d2d70d879
1 changed files with 1 additions and 1 deletions
--- a/migen/fhdl/simplify.py
+++ b/migen/fhdl/simplify.py
@ -41,7 +41,7 @@ class FullMemoryWE(ModuleTransformer):
                            re=port.re,
                            we_granularity=0,
                            mode=port.mode,
-                            clock_domain=port.clock)
+                            clock_domain=port.clock.cd)
                        newmem.ports.append(newport)
                        newspecials.add(newport)
                self.replacments[orig] = newmems