sim/core: fix Cat bitshift

2015-10-19 16:07:45 +08:00 · 2015-10-19 16:07:45 +08:00 · 6d6f91a02b
parent 28962ff438
commit 6d6f91a02b
1 changed files with 2 additions and 1 deletions
--- a/migen/sim/core.py
+++ b/migen/sim/core.py
@ -156,10 +156,11 @@ class Evaluator:
                value -= 2**node.nbits
            self.modifications[node] = value
        elif isinstance(node, Cat):
+            nbits = 0
            for element in node.l:
+                value >>= nbits
                nbits = len(element)
                self.assign(element, value & (2**nbits-1))
-                value >>= nbits
        elif isinstance(node, _Slice):
            full_value = self.eval(node.value, True)
            # clear bits assigned to by the slice