Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

cores/pwm: add CSR descriptions.

This commit is contained in:
Florent Kermarrec 2020-03-11 10:38:28 +01:00
parent cbc1f5949d
commit 6d861c6e57
1 changed files with 7 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
litex/soc/cores/pwm.py
View File

@ -49,9 +49,13 @@ class PWM(Module, AutoCSR):
self.add_csr(clock_domain) self.add_csr(clock_domain)
def add_csr(self, clock_domain): def add_csr(self, clock_domain):
self._enable = CSRStorage() self._enable = CSRStorage(description="""PWM Enable.\n
self._width = CSRStorage(32) Write ``1`` to enable PWM.""")
self._period = CSRStorage(32) self._width = CSRStorage(32, description="""PWM Width.\n
Defines the *Duty cycle* of the PWM. PWM is active high for *Width* ``{cd}_clk`` cycles and
active low for *Period - Width* ``{cd}_clk`` cycles.""".format(cd=clock_domain))
self._period = CSRStorage(32, description="""PWM Period.\n
Defines the *Period* of the PWM in ``{cd}_clk`` cycles.""".format(cd=clock_domain))
n = 0 if clock_domain == "sys" else 2 n = 0 if clock_domain == "sys" else 2
self.specials += [ self.specials += [