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gen/fhdl/verilog: Fix #1777.

This commit is contained in:
Marcus Comstedt 2023-09-14 17:49:44 +02:00
parent a2c2c211c5
commit 6da1482336
1 changed files with 7 additions and 3 deletions
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10
litex/gen/fhdl/verilog.py
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@ -377,11 +377,15 @@ def _print_attribute(attr, attr_translate):
# MODULE #
# ------------------------------------------------------------------------------------------------ #
def _use_wire(stmts):
return (len(stmts) == 1 and isinstance(stmts[0], _Assign) and
not isinstance(stmts[0].l, _Slice))
def _list_comb_wires(f):
r = set()
groups = group_by_targets(f.comb)
for g in groups:
if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
if _use_wire(g[1]):
r |= g[0]
return r
@ -460,7 +464,7 @@ def _print_combinatorial_logic_sim(f, ns):
for n, (t, stmts) in enumerate(target_stmt_map.items()):
assert isinstance(t, Signal)
if len(stmts) == 1 and isinstance(stmts[0], _Assign):
if _use_wire(stmts):
r += "assign " + _print_node(ns, _AT_BLOCKING, 0, stmts[0])
else:
r += "always @(*) begin\n"
@ -476,7 +480,7 @@ def _print_combinatorial_logic_synth(f, ns):
groups = group_by_targets(f.comb)
for n, g in enumerate(groups):
if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
if _use_wire(g[1]):
r += "assign " + _print_node(ns, _AT_BLOCKING, 0, g[1][0])
else:
r += "always @(*) begin\n"