Implement IRQ software support for RISC-V.
Well, at least PicoRV32-specific. Turns out there is no RISC-V specification for simple microcontroller-like interrupts, so PicoRV32 implements its' own based on custom opcodes. It's somewhat esoteric, and for example doesn't offer a global interrupt enable/disable. For this we implement a thin wrapper in assembly and then expose it via a few helpers in irq.h.
This commit is contained in:
Sergiusz Bazanski
parent
2108c97b9b
commit
6daf3eabc5
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@ -5,6 +5,27 @@
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extern "C" {
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#endif
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#ifdef __riscv
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// PicoRV32 has a very limited interrupt support, implemented via custom
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// instructions. It also doesn't have a global interrupt enable/disable, so
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// we have to emulate it via saving and restoring a mask and using 0/~1 as a
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// hardware mask.
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// Due to all this somewhat low-level mess, all of the glue is implementein
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// the RiscV crt0, and this header is kept as a thin wrapper. Since interrupts
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// managed by this layer, do not call interrupt instructions directly, as the
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// state will go out of sync with the hardware.
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// Read only.
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extern unsigned int _irq_pending;
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// Read only.
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extern unsigned int _irq_mask;
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// Read only.
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extern unsigned int _irq_enabled;
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extern void _irq_enable(void);
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extern void _irq_disable(void);
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extern void _irq_setmask(unsigned int);
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#endif
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#ifdef __or1k__
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#include <system.h>
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#endif
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@ -17,9 +38,8 @@ static inline unsigned int irq_getie(void)
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return ie;
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#elif defined (__or1k__)
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return !!(mfspr(SPR_SR) & SPR_SR_IEE);
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#elif defined (__riscv__)
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/* FIXME */
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return 0;
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#elif defined (__riscv)
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return _irq_enabled != 0;
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#else
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#error Unsupported architecture
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#endif
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@ -34,9 +54,11 @@ static inline void irq_setie(unsigned int ie)
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
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else
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
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#elif defined (__riscv__)
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/* FIXME */
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return 0;
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#elif defined (__riscv)
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if (ie & 0x1)
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_irq_enable();
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else
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_irq_disable();
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#else
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#error Unsupported architecture
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#endif
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@ -50,9 +72,10 @@ static inline unsigned int irq_getmask(void)
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return mask;
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#elif defined (__or1k__)
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return mfspr(SPR_PICMR);
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#elif defined (__riscv__)
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/* FIXME */
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return 0;
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#elif defined (__riscv)
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// PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
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// LiteX sees things.
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return ~_irq_mask;
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#else
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#error Unsupported architecture
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#endif
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@ -64,9 +87,10 @@ static inline void irq_setmask(unsigned int mask)
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__asm__ __volatile__("wcsr IM, %0" : : "r" (mask));
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#elif defined (__or1k__)
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mtspr(SPR_PICMR, mask);
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#elif defined (__riscv__)
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/* FIXME */
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return 0;
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#elif defined (__riscv)
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// PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
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// LiteX sees things.
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_irq_setmask(~mask);
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#else
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#error Unsupported architecture
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#endif
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@ -80,9 +104,8 @@ static inline unsigned int irq_pending(void)
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return pending;
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#elif defined (__or1k__)
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return mfspr(SPR_PICSR);
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#elif defined (__riscv__)
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/* FIXME */
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return 0;
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#elif defined (__riscv)
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return _irq_pending;
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#else
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#error Unsupported architecture
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#endif
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@ -1,5 +1,145 @@
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/*
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* Copyright 2018, Serge Bazanski <serge@bazanski.pl>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted.
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*/
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#include "picorv32-extraops.S"
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/*
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* Interrupt vector.
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*/
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.global _start
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_start:
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.org 0x00000000 # Reset
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j _crt0
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.org 0x00000010 # IRQ
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_irq_vector:
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j _irq
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/*
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* IRQ handler, branched to from the vector.
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*/
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_irq:
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/* save x1/x2 to q1/q2 */
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picorv32_setq_insn(q2, x1)
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picorv32_setq_insn(q3, x2)
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/* use x1 to index into irq_regs */
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lui x1, %hi(irq_regs)
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addi x1, x1, %lo(irq_regs)
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/* use x2 as scratch space for saving registers */
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/* q0 (== x1), q2(== x2), q3 */
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picorv32_getq_insn(x2, q0)
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sw x2, 0*4(x1)
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picorv32_getq_insn(x2, q2)
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sw x2, 1*4(x1)
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picorv32_getq_insn(x2, q3)
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sw x2, 2*4(x1)
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/* save x3 - x31 */
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sw x3, 3*4(x1)
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sw x4, 4*4(x1)
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sw x5, 5*4(x1)
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sw x6, 6*4(x1)
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sw x7, 7*4(x1)
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sw x8, 8*4(x1)
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sw x9, 9*4(x1)
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sw x10, 10*4(x1)
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sw x11, 11*4(x1)
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sw x12, 12*4(x1)
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sw x13, 13*4(x1)
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sw x14, 14*4(x1)
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sw x15, 15*4(x1)
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sw x16, 16*4(x1)
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sw x17, 17*4(x1)
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sw x18, 18*4(x1)
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sw x19, 19*4(x1)
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sw x20, 20*4(x1)
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sw x21, 21*4(x1)
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sw x22, 22*4(x1)
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sw x23, 23*4(x1)
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sw x24, 24*4(x1)
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sw x25, 25*4(x1)
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sw x26, 26*4(x1)
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sw x27, 27*4(x1)
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sw x28, 28*4(x1)
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sw x29, 29*4(x1)
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sw x30, 30*4(x1)
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sw x31, 31*4(x1)
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/* update _irq_pending to the currently pending interrupts */
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picorv32_getq_insn(t0, q1)
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la t1, (_irq_pending)
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sw t0, 0(t1)
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/* prepare C handler stack */
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lui sp, %hi(_irq_stack)
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addi sp, sp, %lo(_irq_stack)
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/* call C handler */
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jal ra, isr
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/* use x1 to index into irq_regs */
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lui x1, %hi(irq_regs)
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addi x1, x1, %lo(irq_regs)
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/* restore q0 - q2 */
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lw x2, 0*4(x1)
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picorv32_setq_insn(q0, x2)
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lw x2, 1*4(x1)
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picorv32_setq_insn(q1, x2)
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lw x2, 2*4(x1)
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picorv32_setq_insn(q2, x2)
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/* restore x3 - x31 */
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lw x3, 3*4(x1)
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lw x4, 4*4(x1)
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lw x5, 5*4(x1)
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lw x6, 6*4(x1)
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lw x7, 7*4(x1)
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lw x8, 8*4(x1)
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lw x9, 9*4(x1)
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lw x10, 10*4(x1)
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lw x11, 11*4(x1)
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lw x12, 12*4(x1)
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lw x13, 13*4(x1)
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lw x14, 14*4(x1)
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lw x15, 15*4(x1)
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lw x16, 16*4(x1)
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lw x17, 17*4(x1)
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lw x18, 18*4(x1)
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lw x19, 19*4(x1)
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lw x20, 20*4(x1)
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lw x21, 21*4(x1)
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lw x22, 22*4(x1)
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lw x23, 23*4(x1)
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lw x24, 24*4(x1)
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lw x25, 25*4(x1)
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lw x26, 26*4(x1)
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lw x27, 27*4(x1)
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lw x28, 28*4(x1)
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lw x29, 29*4(x1)
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lw x30, 30*4(x1)
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lw x31, 31*4(x1)
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/* restore x1 - x2 from q registers */
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picorv32_getq_insn(x1, q1)
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picorv32_getq_insn(x2, q2)
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/* return from interrupt */
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picorv32_retirq_insn()
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/*
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* Reset handler, branched to from the vector.
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*/
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_crt0:
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/* zero-initialize all registers */
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addi x1, zero, 0
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addi x2, zero, 0
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@ -33,5 +173,103 @@ _start:
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addi x30, zero, 0
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addi x31, zero, 0
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/* mask all interrupts */
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li t0, 0xffffffff
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picorv32_maskirq_insn(zero, t0)
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/* reflect that in _irq_mask */
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la t1, _irq_mask
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sw t0, 0(t1)
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/* set main stack */
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la sp, _fstack
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/* jump to main */
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jal ra, main
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1:
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/* loop forever */
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j 1b
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/*
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* Enable interrupts by copying the software mask to the hardware mask
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*/
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.global _irq_enable
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_irq_enable:
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/* Set _irq_enabled to true */
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la t0, _irq_enabled
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addi t1, zero, 1
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sw t1, 0(t0)
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/* Set the HW IRQ mask to _irq_mask */
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la t0, _irq_mask
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lw t0, 0(t0)
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picorv32_maskirq_insn(zero, t0)
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ret
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/*
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* Disable interrupts by masking all interrupts (the mask should already be
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* up to date)
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*/
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.global _irq_disable
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_irq_disable:
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/* Mask all IRQs */
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li t0, 0xffffffff
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picorv32_maskirq_insn(zero, t0)
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/* Set _irq_enabled to false */
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la t0, _irq_enabled
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sw zero, (t0)
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ret
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/*
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* Set interrrupt mask.
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* This updates the software mask (for readback and interrupt inable/disable)
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* and the hardware mask.
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* 1 means interrupt is masked (disabled).
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*/
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.global _irq_setmask
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_irq_setmask:
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/* Update _irq_mask */
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la t0, _irq_mask
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sw a0, (t0)
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/* Are interrupts enabled? */
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la t0, _irq_enabled
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lw t0, 0(t0)
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beq t0, zero, 1f
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/* If so, update the HW IRQ mask */
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picorv32_maskirq_insn(zero, a0)
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1:
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ret
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.section .bss
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irq_regs:
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/* saved interrupt registers, x0 - x31 */
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.fill 32,4
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/* interrupt stack */
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.fill 256,4
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_irq_stack:
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/*
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* Bitfield of pending interrupts, updated on ISR entry.
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*/
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.global _irq_pending
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_irq_pending:
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.word 0
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/*
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* Software copy of enabled interrupts. Do not write directly, use
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* _irq_set_mask instead.
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*/
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.global _irq_mask
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_irq_mask:
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.word 0
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/*
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* Software state of global interrupts being enabled or disabled. Do not write
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* directly, use _irq_disable / _irq_enable instead.
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*/
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.global _irq_enabled
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_irq_enabled:
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.word 0
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