soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize
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305b8879de
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6de2713524
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@ -66,66 +66,54 @@ class AXIInterface(Record):
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# AXI Bursts to Beats ------------------------------------------------------------------------------
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class AXIBurst2Beat(Module):
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def __init__(self, ax_burst, ax_beat):
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def __init__(self, ax_burst, ax_beat, capabilities={BURST_FIXED, BURST_INCR, BURST_WRAP}):
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assert BURST_FIXED in capabilities
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# # #
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self.count = count = Signal(8)
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size = Signal(8 + 4)
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offset = Signal(8 + 4)
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beat_count = Signal(8)
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beat_size = Signal(8 + 4)
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beat_offset = Signal(8 + 4)
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beat_wrap = Signal(8 + 4)
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# convert burst size to bytes
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cases = {}
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cases["default"] = size.eq(1024)
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for i in range(10):
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cases[i] = size.eq(2**i)
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self.comb += Case(ax_burst.size, cases)
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# compute parameters
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self.comb += beat_size.eq(1 << ax_burst.size)
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self.comb += beat_wrap.eq(ax_burst.len*beat_size)
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# fsm
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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ax_beat.valid.eq(ax_burst.valid),
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ax_beat.first.eq(1),
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ax_beat.last.eq(ax_burst.len == 0),
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ax_beat.addr.eq(ax_burst.addr),
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# combinatorial logic
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self.comb += [
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ax_beat.valid.eq(ax_burst.valid | ~ax_beat.first),
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ax_beat.first.eq(beat_count == 0),
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ax_beat.last.eq(beat_count == ax_burst.len),
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ax_beat.addr.eq(ax_burst.addr + beat_offset),
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ax_beat.id.eq(ax_burst.id),
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If(ax_beat.valid & ax_beat.ready,
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If(ax_burst.len != 0,
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NextState("BURST2BEAT")
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).Else(
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If(ax_beat.ready,
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If(ax_beat.last,
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ax_burst.ready.eq(1)
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)
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),
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NextValue(count, 1),
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NextValue(offset, size),
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)
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wrap_offset = Signal(8 + 4)
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self.sync += wrap_offset.eq((ax_burst.len - 1)*size)
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fsm.act("BURST2BEAT",
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ax_beat.valid.eq(1),
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ax_beat.first.eq(0),
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ax_beat.last.eq(count == ax_burst.len),
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If((ax_burst.burst == BURST_INCR) |
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(ax_burst.burst == BURST_WRAP),
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ax_beat.addr.eq(ax_burst.addr + offset)
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).Else(
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ax_beat.addr.eq(ax_burst.addr)
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),
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ax_beat.id.eq(ax_burst.id),
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]
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# synchronous logic
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self.sync += [
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If(ax_beat.valid & ax_beat.ready,
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If(ax_beat.last,
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ax_burst.ready.eq(1),
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NextState("IDLE")
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beat_count.eq(0),
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beat_offset.eq(0)
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).Else(
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beat_count.eq(beat_count + 1),
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If(((ax_burst.burst == BURST_INCR) & (BURST_INCR in capabilities)) |
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((ax_burst.burst == BURST_WRAP) & (BURST_WRAP in capabilities)),
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beat_offset.eq(beat_offset + beat_size)
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)
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),
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NextValue(count, count + 1),
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NextValue(offset, offset + size),
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If(ax_burst.burst == BURST_WRAP,
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If(offset == wrap_offset,
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NextValue(offset, 0)
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)
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If((ax_burst.burst == BURST_WRAP) & (BURST_WRAP in capabilities),
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If(beat_offset == beat_wrap,
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beat_offset.eq(0)
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)
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)
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)
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]
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# AXI to Wishbone ----------------------------------------------------------------------------------
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@ -23,7 +23,7 @@ class Burst:
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offset = i*2**(self.size)
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r += [Beat(self.addr + offset)]
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elif self.type == BURST_WRAP:
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offset = (i*2**(self.size))%((2**self.size)*(self.len))
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offset = (i*2**(self.size))%((2**self.size)*(self.len + 1))
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r += [Beat(self.addr + offset)]
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else:
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r += [Beat(self.addr)]
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