gen/fhdl/module: Fix CSR clock domain renaming to cores converted to LiteXModule, thanks @smunaut.

CHANGES.md

@@ -10,6 +10,7 @@
 	- cpu/vexriscv_smp    : Fixed compilation with Gowin toolchain (ex for Tang Nano 20K Linux).
 	- liteiclink/serwb    : Fixed 7-Series initialization corner cases.
 	- liteeth/core/icmp   : Fixed length check on LiteEthICMPEcho before passing data to buffer.
+	- LiteXModule/CSR     : Fixed CSR collection order causing CSR clock domain to be changed.
 
 	[> Added
 	--------

litex/gen/fhdl/module.py

@@ -8,7 +8,7 @@ from migen import *
 from migen.fhdl.module import _ModuleProxy
 from migen.fhdl.specials import Special
 
-from litex.soc.interconnect.csr import AutoCSR
+from litex.soc.interconnect.csr import _CSRBase, AutoCSR
 from litex.soc.integration.doc import AutoDoc
 
 # LiteX Module -------------------------------------------------------------------------------------
@@ -21,7 +21,8 @@ class LiteXModule(Module, AutoCSR, AutoDoc):
                 raise AttributeError("Attempted to assign special Module property - use += instead")
         # LiteX fix-up: Automatically collect specials/submodules/clock_domains:
         # - m.module_x  = .. equivalent of Migen's m.submodules.module_x = ..
-        elif isinstance(value, Module)      and ((name, value) not in m._submodules):
+        # Note: Do an exception for CSRs that have a specific collection mechanism.
+        elif (isinstance(value, Module)      and ((name, value) not in m._submodules) and (not isinstance(value, _CSRBase))):
             setattr(m.submodules, name, value)
         # - m.special_x = .. equivalent of Migen's m.specials.special_x  = ..
         elif isinstance(value, Special)     and (value not in m._fragment.specials):