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platforms/papilio_pro: fix clock signal handling

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This commit is contained in:
Sebastien Bourdeauducq 2013-11-24 23:42:31 +01:00
parent c514fdc4a3
commit 6e48682a5e
1 changed files with 10 additions and 1 deletions
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11
mibuild/platforms/papilio_pro.py
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@ -41,4 +41,13 @@ _io = [
class Platform(XilinxISEPlatform):
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io,
lambda p: CRG_SE(p, "clk32", None, 31.25))
lambda p: CRG_SE(p, "clk32", None))
def do_finalize(self, fragment):
try:
self.add_platform_command("""
NET "{clk32}" TNM_NET = "GRPclk32";
TIMESPEC "TSclk32" = PERIOD "GRPclk32" 31.25 ns HIGH 50%;
""", clk32=self.lookup_request("clk32"))
except ConstraintError:
pass