add edif build routines

This commit is contained in:
Nina Engelhardt 2013-08-02 17:10:33 +02:00 committed by Sebastien Bourdeauducq
parent 275a7ea94a
commit 6e64016885
2 changed files with 54 additions and 23 deletions

View File

@ -4,7 +4,7 @@ import os, argparse
from migen.fhdl.std import *
from migen.fhdl.structure import _Fragment
from migen.genlib.record import Record
from migen.fhdl import verilog
from migen.fhdl import verilog, edif
from mibuild import tools
@ -194,6 +194,18 @@ class GenericPlatform:
if language is not None:
self.add_source(os.path.join(root, filename), language)
def _resolve_signals(self, vns):
# resolve signal names in constraints
sc = self.constraint_manager.get_sig_constraints()
named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]
# resolve signal names in platform commands
pc = self.constraint_manager.get_platform_commands()
named_pc = []
for template, args in pc:
name_dict = dict((k, vns.get_name(sig)) for k, sig in args.items())
named_pc.append(template.format(**name_dict))
return named_sc, named_pc
def get_verilog(self, fragment, **kwargs):
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
@ -215,19 +227,21 @@ class GenericPlatform:
# generate Verilog
src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(),
return_ns=True, create_clock_domains=False, **kwargs)
# resolve signal names in constraints
sc = self.constraint_manager.get_sig_constraints()
named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]
# resolve signal names in platform commands
pc = self.constraint_manager.get_platform_commands()
named_pc = []
for template, args in pc:
name_dict = dict((k, vns.get_name(sig)) for k, sig in args.items())
named_pc.append(template.format(**name_dict))
named_sc, named_pc = self._resolve_signals(vns)
finally:
self.constraint_manager.restore(backup)
return src, named_sc, named_pc
def get_edif(self, fragment, cell_library, vendor, device, **kwargs):
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
# finalize
self.finalize(fragment)
# generate EDIF
src, vns = edif.convert(fragment, self.constraint_manager.get_io_signals(), cell_library, vendor, device, return_ns=True, **kwargs)
named_sc, named_pc = self._resolve_signals(vns)
return src, named_sc, named_pc
def build(self, fragment):
raise NotImplementedError("GenericPlatform.build must be overloaded")

View File

@ -95,7 +95,7 @@ def _is_valid_version(path, v):
except:
return False
def _run_ise(build_name, ise_path, source):
def _run_ise(build_name, ise_path, source, mode="verilog"):
if sys.platform == "win32" or sys.platform == "cygwin":
source = False
build_script_contents = "# Autogenerated by mibuild\nset -e\n"
@ -105,10 +105,15 @@ def _run_ise(build_name, ise_path, source):
bits = struct.calcsize("P")*8
xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (ise_path, tools_version, bits)
build_script_contents += "source " + xilinx_settings_file + "\n"
if mode == "edif":
build_script_contents += """
ngdbuild -uc {build_name}.ucf {build_name}.edif {build_name}.ngd""".format(build_name=build_name)
else:
build_script_contents += """
xst -ifn {build_name}.xst
ngdbuild -uc {build_name}.ucf {build_name}.ngc {build_name}.ngd"""
build_script_contents += """
xst -ifn {build_name}.xst
ngdbuild -uc {build_name}.ucf {build_name}.ngc {build_name}.ngd
map -ol high -w -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf
par -ol high -w {build_name}_map.ncd {build_name}.ncd {build_name}.pcf
bitgen -g LCK_cycle:6 -g Binary:Yes -w {build_name}.ncd {build_name}.bit
@ -149,19 +154,31 @@ class XilinxISEPlatform(GenericPlatform):
so.update(special_overrides)
return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
def get_edif(self, fragment, **kwargs):
return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs)
def build(self, fragment, build_dir="build", build_name="top",
ise_path="/opt/Xilinx", source=True, run=True):
ise_path="/opt/Xilinx", source=True, run=True, mode="verilog"):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
v_src, named_sc, named_pc = self.get_verilog(fragment)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
_build_files(self.device, sources, named_sc, named_pc, build_name)
if run:
_run_ise(build_name, ise_path, source)
if mode == "verilog":
v_src, named_sc, named_pc = self.get_verilog(fragment)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
_build_files(self.device, sources, named_sc, named_pc, build_name)
if run:
_run_ise(build_name, ise_path, source, mode="verilog")
if mode == "edif":
e_src, named_sc, named_pc = self.get_edif(fragment)
e_file = build_name + ".edif"
tools.write_to_file(e_file, e_src)
sources = self.sources + [(e_file, "edif")]
tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
if run:
_run_ise(build_name, ise_path, source, mode="edif")
os.chdir("..")
def build_arg_ns(self, ns, *args, **kwargs):