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soc/add_bus_master: Use name where possible to avoid automatic naming and improve log readability.

This commit is contained in:
Florent Kermarrec 2023-07-20 15:15:44 +02:00
parent f6da67fb38
commit 6e78db6767
2 changed files with 7 additions and 7 deletions
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12
litex/soc/integration/soc.py
View File

@ -1746,7 +1746,7 @@ class LiteXSoC(SoC):
self.check_if_exists(name) self.check_if_exists(name)
etherbone = LiteEthEtherbone(ethcore.udp, udp_port, buffer_depth=buffer_depth, cd=etherbone_cd) etherbone = LiteEthEtherbone(ethcore.udp, udp_port, buffer_depth=buffer_depth, cd=etherbone_cd)
self.add_module(name=name, module=etherbone) self.add_module(name=name, module=etherbone)
self.bus.add_master(master=etherbone.wishbone.bus) self.bus.add_master(name=name, master=etherbone.wishbone.bus)
# Timing constraints # Timing constraints
if with_timing_constraints: if with_timing_constraints:
@ -1862,7 +1862,7 @@ class LiteXSoC(SoC):
self.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness) self.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
self.comb += self.sdcore.source.connect(self.sdblock2mem.sink) self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
dma_bus.add_master("sdblock2mem", master=bus) dma_bus.add_master(name="sdblock2mem", master=bus)
# Mem2Block DMA. # Mem2Block DMA.
if "write" in mode: if "write" in mode:
@ -1870,7 +1870,7 @@ class LiteXSoC(SoC):
self.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness) self.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness)
self.comb += self.sdmem2block.source.connect(self.sdcore.sink) self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
dma_bus.add_master("sdmem2block", master=bus) dma_bus.add_master(name="sdmem2block", master=bus)
# Interrupts. # Interrupts.
self.sdirq = EventManager() self.sdirq = EventManager()
@ -1935,7 +1935,7 @@ class LiteXSoC(SoC):
bus = bus, bus = bus,
endianness = self.cpu.endianness) endianness = self.cpu.endianness)
dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
dma_bus.add_master("sata_sector2mem", master=bus) dma_bus.add_master(name="sata_sector2mem", master=bus)
# Mem2Sector DMA. # Mem2Sector DMA.
if "write" in mode: if "write" in mode:
@ -1945,7 +1945,7 @@ class LiteXSoC(SoC):
port = self.sata_crossbar.get_port(), port = self.sata_crossbar.get_port(),
endianness = self.cpu.endianness) endianness = self.cpu.endianness)
dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
dma_bus.add_master("sata_mem2sector", master=bus) dma_bus.add_master(name="sata_mem2sector", master=bus)
# Interrupts. # Interrupts.
self.sata_irq = EventManager() self.sata_irq = EventManager()
@ -2001,7 +2001,7 @@ class LiteXSoC(SoC):
self.check_if_exists(f"{name}_mmap") self.check_if_exists(f"{name}_mmap")
mmap = LitePCIeWishboneMaster(self.pcie_endpoint, base_address=self.mem_map["csr"]) mmap = LitePCIeWishboneMaster(self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_module(name=f"{name}_mmap", module=mmap) self.add_module(name=f"{name}_mmap", module=mmap)
self.bus.add_master(master=mmap.wishbone) self.bus.add_master(name=f"{name}_mmap", master=mmap.wishbone)
# MSI. # MSI.
if with_msi: if with_msi:

2
litex/tools/litex_sim.py
View File

@ -255,7 +255,7 @@ class SimSoC(SoCCore):
self.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8) self.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8)
# Etherbone # Etherbone
self.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master") self.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master")
self.bus.add_master(master=self.etherbone.wishbone.bus) self.bus.add_master(name="etherbone", master=self.etherbone.wishbone.bus)
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------
elif with_ethernet: elif with_ethernet: