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pipistrello: fix FPGA speed grade

This commit is contained in:
Yann Sionneau 2015-06-14 23:19:27 +02:00
parent 33b536e505
commit 6e876c63ad
1 changed files with 1 additions and 1 deletions
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2
mibuild/platforms/pipistrello.py
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@ -130,7 +130,7 @@ class Platform(XilinxPlatform):
default_clk_period = 20
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io, _connectors)
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
def create_programmer(self):