fhdl/verilog: create clock domains in deterministic order

2015-11-05 15:06:33 +08:00 · 2015-11-05 15:06:33 +08:00 · 6f5bf0292e
parent 180ba95dd4
commit 6f5bf0292e
1 changed files with 1 additions and 1 deletions
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@ -323,7 +323,7 @@ def convert(f, ios=None, name="top",
    if ios is None:
        ios = set()

-    for cd_name in list_clock_domains(f):
+    for cd_name in sorted(list_clock_domains(f)):
        try:
            f.clock_domains[cd_name]
        except KeyError: