host: remove cpuif (we use the one from MiSoC) and some clean up

This commit is contained in:
Florent Kermarrec 2015-01-23 15:31:25 +01:00
parent 9a3e9f86cf
commit 6f7d85b95c
6 changed files with 17 additions and 31 deletions

View File

@ -1,7 +1,4 @@
from migen.fhdl.std import *
from migen.fhdl.specials import Special
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.fhdl import verilog
from migen.bank.description import *
from migen.actorlib.fifo import AsyncFIFO
@ -88,14 +85,12 @@ class LiteScopeLA(Module, AutoCSR):
self.comb += sink.connect(recorder.dat_sink)
def export(self, layout, vns, filename):
r = ""
def format_line(*args):
return ",".join(args) + "\n"
r = ""
r += format_line("config", "width", str(self.width))
r += format_line("config", "depth", str(self.depth))
r += format_line("config", "with_rle", str(int(self.with_rle)))
for e in layout:
r += format_line("layout", vns.get_name(e), str(flen(e)))
write_to_file(filename, r)

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@ -1,11 +0,0 @@
from migen.bank.description import CSRStatus
def get_csr_csv(csr_base, bank_array):
r = ""
for name, csrs, mapaddr, rmap in bank_array.banks:
reg_base = csr_base + 0x800*mapaddr
for csr in csrs:
nr = (csr.size + 7)//8
r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, reg_base, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
reg_base += 4*nr
return r

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@ -13,8 +13,10 @@ def write_b(uart, data):
uart.write(pack('B',data))
class LiteScopeUART2WBDriver:
WRITE_CMD = 0x01
READ_CMD = 0x02
cmds = {
"write" : 0x01,
"read" : 0x02
}
def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False):
self.port = port
self.baudrate = str(baudrate)
@ -42,7 +44,7 @@ class LiteScopeUART2WBDriver:
def read(self, addr, burst_length=1):
self.uart.flushInput()
write_b(self.uart, self.READ_CMD)
write_b(self.uart, self.cmds["read"])
write_b(self.uart, burst_length)
addr = addr//4
write_b(self.uart, (addr & 0xff000000) >> 24)
@ -68,7 +70,7 @@ class LiteScopeUART2WBDriver:
burst_length = len(data)
else:
burst_length = 1
write_b(self.uart, self.WRITE_CMD)
write_b(self.uart, self.cmds["write"])
write_b(self.uart, burst_length)
addr = addr//4
write_b(self.uart, (addr & 0xff000000) >> 24)

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@ -11,7 +11,7 @@ from mibuild.xilinx_common import *
from misoclib.gensoc import cpuif
from litesata.common import *
from litescope.common import *
def _import(default, name):
return importlib.import_module(default + "." + name)