host: remove cpuif (we use the one from MiSoC) and some clean up

litescope/frontend/la.py

@@ -1,7 +1,4 @@
 from migen.fhdl.std import *
-from migen.fhdl.specials import Special
-from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.fhdl import verilog
 from migen.bank.description import *
 from migen.actorlib.fifo import AsyncFIFO
 
@@ -88,14 +85,12 @@ class LiteScopeLA(Module, AutoCSR):
 			self.comb += sink.connect(recorder.dat_sink)
 
 	def export(self, layout, vns, filename):
-		r = ""
 		def format_line(*args):
 			return ",".join(args) + "\n"
-
+		r = ""
 		r += format_line("config", "width", str(self.width))
 		r += format_line("config", "depth", str(self.depth))
 		r += format_line("config", "with_rle", str(int(self.with_rle)))
-
 		for e in layout:
 			r += format_line("layout", vns.get_name(e), str(flen(e)))
 		write_to_file(filename, r)

litescope/host/cpuif.py

@@ -1,11 +0,0 @@
-from migen.bank.description import CSRStatus
-
-def get_csr_csv(csr_base, bank_array):
-	r = ""
-	for name, csrs, mapaddr, rmap in bank_array.banks:
-		reg_base = csr_base + 0x800*mapaddr
-		for csr in csrs:
-			nr = (csr.size + 7)//8
-			r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, reg_base, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
-			reg_base += 4*nr
-	return r

litescope/host/driver.py

@@ -13,8 +13,10 @@ def write_b(uart, data):
 	uart.write(pack('B',data))
 
 class LiteScopeUART2WBDriver:
-	WRITE_CMD  = 0x01
-	READ_CMD   = 0x02
+	cmds = {
+		"write"	: 0x01,
+		"read"	: 0x02
+	}
 	def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False):
 		self.port = port
 		self.baudrate = str(baudrate)
@@ -42,7 +44,7 @@ class LiteScopeUART2WBDriver:
 
 	def read(self, addr, burst_length=1):
 		self.uart.flushInput()
-		write_b(self.uart, self.READ_CMD)
+		write_b(self.uart, self.cmds["read"])
 		write_b(self.uart, burst_length)
 		addr = addr//4
 		write_b(self.uart, (addr & 0xff000000) >> 24)
@@ -68,7 +70,7 @@ class LiteScopeUART2WBDriver:
 			burst_length = len(data)
 		else:
 			burst_length = 1
-		write_b(self.uart, self.WRITE_CMD)
+		write_b(self.uart, self.cmds["write"])
 		write_b(self.uart, burst_length)
 		addr = addr//4
 		write_b(self.uart, (addr & 0xff000000) >> 24)

litescope/host/dump.py

@@ -77,16 +77,16 @@ class Var:
 		self.val = default
 		self.values = values
 		self.vcd_id = None
-		
+
 	def set_vcd_id(self, s):
 		self.vcd_id = s
-	
+
 	def __len__(self):
 		return len(self.values)
 
 	def change(self, cnt):
 		r = ""
-		try : 
+		try :
 			if self.values[cnt+1] != self.val:
 				r += "b"
 				r += dec2bin(self.values[cnt+1], self.width)
@@ -102,7 +102,7 @@ class Dump:
 	def __init__(self):
 		self.vars = []
 		self.vcd_id = "!"
-		
+
 	def add(self, var):
 		var.set_vcd_id(self.vcd_id)
 		self.vcd_id = chr(ord(self.vcd_id)+1)
@@ -113,7 +113,7 @@ class Dump:
 		for s, n in layout:
 			self.add(Var(s, n, var[i:i+n]))
 			i += n
-	
+
 	def __len__(self):
 		l = 0
 		for var in self.vars:
@@ -301,7 +301,7 @@ def main():
 	dump.add(Var("foo2", 2, [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
 	ramp = [i%128 for i in range(1024)]
 	dump.add(Var("ramp", 16, ramp))
-	
+
 	VCDExport(dump).write("mydump.vcd")
 	CSVExport(dump).write("mydump.csv")
 	PYExport(dump).write("mydump.py")

litescope/host/truthtable.py

@@ -1,5 +1,5 @@
 import os
-import re 
+import re
 import sys
 
 def is_number(x):
@@ -32,7 +32,7 @@ def gen_truth_table(s):
 		for j in range(2**width):
 			stim_op.append((int(j/(2**i)))%2)
 		stim.append(stim_op)
-	
+
 	truth_table = []
 	for i in range(2**width):
 		for j in range(width):
@@ -42,6 +42,6 @@ def gen_truth_table(s):
 
 def main():
 	print(gen_truth_table("(A&B&C)|D"))
-	
+
 if __name__ == '__main__':
 	main()

make.py

@@ -11,7 +11,7 @@ from mibuild.xilinx_common import *
 
 from misoclib.gensoc import cpuif
 
-from litesata.common import *
+from litescope.common import *
 
 def _import(default, name):
 	return importlib.import_module(default + "." + name)