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fhdl/verilog: tristate outputs are always wire

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This commit is contained in:
Sebastien Bourdeauducq 2013-03-06 11:30:52 +01:00
parent 9b4ca987e0
commit 6fa30053bf
1 changed files with 3 additions and 3 deletions
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6
migen/fhdl/verilog.py
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@ -135,10 +135,10 @@ def _list_comb_wires(f):
def _printheader(f, ios, name, ns):
sigs = list_signals(f) | list_special_ios(f, True, True, True)
it_mem_outs = list_special_ios(f, False, True, False)
special_outs = list_special_ios(f, False, True, True)
inouts = list_special_ios(f, False, False, True)
targets = list_targets(f) | it_mem_outs
wires = _list_comb_wires(f) | it_mem_outs
targets = list_targets(f) | special_outs
wires = _list_comb_wires(f) | special_outs
r = "module " + name + "(\n"
firstp = True
for sig in sorted(ios, key=lambda x: x.huid):