build: remove edif support
This commit is contained in:
Florent Kermarrec
parent
e407a1cdda
commit
6fd0b73817
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@ -3,7 +3,7 @@ import os
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from litex.gen.fhdl.structure import Signal
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from litex.gen.genlib.record import Record
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from litex.gen.genlib.io import CRG
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from litex.gen.fhdl import verilog, edif
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from litex.gen.fhdl import verilog
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from litex.build import tools
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@ -330,12 +330,6 @@ class GenericPlatform:
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self.constraint_manager.get_io_signals(),
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create_clock_domains=False, **kwargs)
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def get_edif(self, fragment, cell_library, vendor, device, **kwargs):
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return edif.convert(
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fragment,
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self.constraint_manager.get_io_signals(),
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cell_library, vendor, device, **kwargs)
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def build(self, fragment):
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raise NotImplementedError("GenericPlatform.build must be overloaded")
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@ -96,11 +96,9 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
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if source:
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settings = common.settings(ise_path, ver, "ISE_DS")
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build_script_contents += source_cmd + settings + "\n"
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if mode == "edif":
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ext = "edif"
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else:
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ext = "ngc"
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build_script_contents += """
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ext = "ngc"
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build_script_contents += """
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xst -ifn {build_name}.xst
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"""
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@ -171,18 +169,6 @@ class XilinxISEToolchain:
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isemode = "edif"
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ngdbuild_opt += "-p " + platform.device
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if mode == "mist":
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from mist import synthesize
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synthesize(fragment, platform.constraint_manager.get_io_signals())
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if mode == "edif" or mode == "mist":
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e_output = platform.get_edif(fragment)
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vns = e_output.ns
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named_sc, named_pc = platform.resolve_signals(vns)
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e_file = build_name + ".edif"
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e_output.write(e_file)
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isemode = "edif"
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tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
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if run:
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_run_ise(build_name, toolchain_path, source, isemode,
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@ -21,9 +21,6 @@ class XilinxPlatform(GenericPlatform):
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so.update(special_overrides)
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return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
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def get_edif(self, fragment, **kwargs):
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return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs)
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def build(self, *args, **kwargs):
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return self.toolchain.build(self, *args, **kwargs)
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@ -1,213 +0,0 @@
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from collections import OrderedDict, namedtuple
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from litex.gen.fhdl.structure import *
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from litex.gen.fhdl.namer import build_namespace
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from litex.gen.fhdl.tools import list_special_ios
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from litex.gen.fhdl.structure import _Fragment
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from litex.gen.fhdl.conv_output import ConvOutput
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_Port = namedtuple("_Port", "name direction")
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_Cell = namedtuple("_Cell", "name ports")
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_Property = namedtuple("_Property", "name value")
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_Instance = namedtuple("_Instance", "name cell properties")
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_NetBranch = namedtuple("_NetBranch", "portname instancename")
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def _write_cells(cells):
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r = ""
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for cell in cells:
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r += """
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(cell {0.name}
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(cellType GENERIC)
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(view view_1
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(viewType NETLIST)
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(interface""".format(cell)
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for port in cell.ports:
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r += """
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(port {0.name} (direction {0.direction}))""".format(port)
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r += """
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)
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)
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)"""
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return r
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def _write_io(ios):
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r = ""
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for s in ios:
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r += """
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(port {0.name} (direction {0.direction}))""".format(s)
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return r
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def _write_instantiations(instances, cell_library):
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instantiations = ""
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for instance in instances:
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instantiations += """
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(instance {0.name}
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(viewRef view_1 (cellRef {0.cell} (libraryRef {1})))""".format(instance, cell_library)
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for prop in instance.properties:
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instantiations += """
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(property {0} (string "{1}"))""".format(prop.name, prop.value)
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instantiations += """
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)"""
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return instantiations
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def _write_connections(connections):
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r = ""
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for netname, branches in connections.items():
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r += """
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(net {0}
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(joined""".format(netname)
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for branch in branches:
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r += """
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(portRef {0}{1})""".format(branch.portname, "" if branch.instancename == "" else " (instanceRef {})".format(branch.instancename))
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r += """
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)
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)"""
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return r
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def _write_edif(cells, ios, instances, connections, cell_library, design_name, part, vendor):
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r = """(edif {0}
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(edifVersion 2 0 0)
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(edifLevel 0)
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(keywordMap (keywordLevel 0))
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(external {1}
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(edifLevel 0)
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(technology (numberDefinition))""".format(design_name, cell_library)
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r += _write_cells(cells)
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r += """
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)
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(library {0}_lib
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(edifLevel 0)
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(technology (numberDefinition))
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(cell {0}
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(cellType GENERIC)
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(view view_1
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(viewType NETLIST)
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(interface""".format(design_name)
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r += _write_io(ios)
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r += """
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(designator "{0}")
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)
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(contents""".format(part)
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r += _write_instantiations(instances, cell_library)
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r += _write_connections(connections)
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r += """
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)
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)
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)
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)
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(design {0}
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(cellRef {0} (libraryRef {0}_lib))
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(property PART (string "{1}") (owner "{2}"))
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)
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)""".format(design_name, part, vendor)
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return r
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def _generate_cells(f):
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cell_dict = OrderedDict()
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for special in f.specials:
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if isinstance(special, Instance):
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port_list = []
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for port in special.items:
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if isinstance(port, Instance.Input):
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port_list.append(_Port(port.name, "INPUT"))
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elif isinstance(port, Instance.Output):
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port_list.append(_Port(port.name, "OUTPUT"))
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elif isinstance(port, Instance.InOut):
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port_list.append(_Port(port.name, "INOUT"))
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elif isinstance(port, Instance.Parameter):
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pass
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else:
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raise NotImplementedError("Unsupported instance item")
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if special.of in cell_dict:
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if set(port_list) != set(cell_dict[special.of]):
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raise ValueError("All instances must have the same ports for EDIF conversion")
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else:
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cell_dict[special.of] = port_list
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else:
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raise ValueError("EDIF conversion can only handle synthesized fragments")
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return [_Cell(k, v) for k, v in cell_dict.items()]
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def _generate_instances(f, ns):
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instances = []
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for special in f.specials:
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if isinstance(special, Instance):
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props = []
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for prop in special.items:
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if isinstance(prop, Instance.Input):
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pass
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elif isinstance(prop, Instance.Output):
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pass
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elif isinstance(prop, Instance.InOut):
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pass
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elif isinstance(prop, Instance.Parameter):
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props.append(_Property(name=prop.name, value=prop.value))
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else:
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raise NotImplementedError("Unsupported instance item")
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instances.append(_Instance(name=ns.get_name(special), cell=special.of, properties=props))
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else:
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raise ValueError("EDIF conversion can only handle synthesized fragments")
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return instances
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def _generate_ios(f, ios, ns):
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outs = list_special_ios(f, False, True, False)
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inouts = list_special_ios(f, False, False, True)
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r = []
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for io in ios:
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direction = "OUTPUT" if io in outs else "INOUT" if io in inouts else "INPUT"
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r.append(_Port(name=ns.get_name(io), direction=direction))
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return r
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def _generate_connections(f, ios, ns):
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r = OrderedDict()
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for special in f.specials:
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if isinstance(special, Instance):
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instname = ns.get_name(special)
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for port in special.items:
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if isinstance(port, Instance._IO):
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s = ns.get_name(port.expr)
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if s not in r:
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r[s] = []
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r[s].append(_NetBranch(portname=port.name, instancename=instname))
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elif isinstance(port, Instance.Parameter):
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pass
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else:
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raise NotImplementedError("Unsupported instance item")
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else:
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raise ValueError("EDIF conversion can only handle synthesized fragments")
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for s in ios:
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io = ns.get_name(s)
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if io not in r:
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r[io] = []
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r[io].append(_NetBranch(portname=io, instancename=""))
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return r
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def convert(f, ios, cell_library, vendor, device, name="top"):
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if not isinstance(f, _Fragment):
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f = f.get_fragment()
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if f.comb != [] or f.sync != {}:
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raise ValueError("EDIF conversion can only handle synthesized fragments")
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if ios is None:
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ios = set()
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cells = _generate_cells(f)
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ns = build_namespace(list_special_ios(f, True, True, True))
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instances = _generate_instances(f, ns)
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inouts = _generate_ios(f, ios, ns)
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connections = _generate_connections(f, ios, ns)
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src = _write_edif(cells, inouts, instances, connections, cell_library, name, device, vendor)
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r = ConvOutput()
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r.set_main_source(src)
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r.ns = ns
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return r
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