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uart2wishbone: disconnect rx line from shared pads when bridge is selected 

(avoid CPU crash when we communicate with the bridge)
This commit is contained in:
Florent Kermarrec 2014-08-03 12:26:41 +02:00
parent f4e6cebab2
commit 6ffed70b59
2 changed files with 27 additions and 12 deletions
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1
miscope/host/uart2wishbone.py
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@ -32,6 +32,7 @@ class Uart2Wishbone:
self.regs.uart2wb_sel.write(0) self.regs.uart2wb_sel.write(0)
except: except:
pass pass
self.uart.flushOutput()
self.uart.close() self.uart.close()
def read(self, addr, burst_length=1): def read(self, addr, burst_length=1):

38
miscope/uart2wishbone.py
View File

@ -136,18 +136,32 @@ class UARTPads:
self.tx = Signal() self.tx = Signal()
class UARTMux(Module): class UARTMux(Module):
def __init__(self, pads, nb): def __init__(self, pads):
self.sel = Signal(max=nb) self.sel = Signal(max=2)
self.pads = [UARTPads() for i in range(nb)] self.shared_pads = UARTPads()
self.bridge_pads = UARTPads()
### ###
# Route Rx pad to all modules # Route rx pad:
for i in range(nb): # when sel==0, route it to shared rx and bridge rx
self.comb += self.pads[i].rx.eq(pads.rx) # when sel==1, route it only to bridge rx
self.comb += \
If(self.sel==0,
self.shared_pads.rx.eq(pads.rx),
self.bridge_pads.rx.eq(pads.rx)
).Else(
self.bridge_pads.rx.eq(pads.rx)
)
# Route only selected module to Tx pad # Route tx:
pads_tx = [self.pads[i].tx for i in range(nb)] # when sel==0, route shared tx to pads tx
self.comb += chooser(Cat(pads_tx), self.sel, pads.tx, n=nb) # when sel==1, route bridge tx to pads tx
self.comb += \
If(self.sel==0,
pads.tx.eq(self.shared_pads.tx)
).Else(
pads.tx.eq(self.bridge_pads.tx)
)
class UART2Wishbone(Module, AutoCSR): class UART2Wishbone(Module, AutoCSR):
WRITE_CMD = 0x01 WRITE_CMD = 0x01
@ -161,9 +175,9 @@ class UART2Wishbone(Module, AutoCSR):
### ###
if share_uart: if share_uart:
self.submodules.uart_mux = UARTMux(pads, 2) self.submodules.uart_mux = UARTMux(pads)
self.submodules.uart = UART(self.uart_mux.pads[1], clk_freq, baud) self.submodules.uart = UART(self.uart_mux.bridge_pads, clk_freq, baud)
self.shared_pads = self.uart_mux.pads[0] self.shared_pads = self.uart_mux.shared_pads
self.comb += self.uart_mux.sel.eq(self._sel.storage) self.comb += self.uart_mux.sel.eq(self._sel.storage)
else: else:
self.submodules.uart = UART(pads, clk_freq, baud) self.submodules.uart = UART(pads, clk_freq, baud)