interconnect/ahb: Simplify AHBInterface and add data_width/address_width parameters.
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@ -22,31 +22,30 @@ class AHBTransferType(IntEnum):
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NONSEQUENTIAL = 2
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NONSEQUENTIAL = 2
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SEQUENTIAL = 3
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SEQUENTIAL = 3
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# AHB Interface ------------------------------------------------------------------------------------
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# AHB Definition -----------------------------------------------------------------------------------
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def ahb_description(data_width, address_width):
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return [
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("addr", address_width, DIR_M_TO_S),
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("burst", 3, DIR_M_TO_S),
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("mastlock", 1, DIR_M_TO_S),
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("prot", 4, DIR_M_TO_S),
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("size", 3, DIR_M_TO_S),
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("trans", 2, DIR_M_TO_S),
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("wdata", data_width, DIR_M_TO_S),
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("write", 1, DIR_M_TO_S),
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("sel", 1, DIR_M_TO_S),
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("rdata", data_width, DIR_S_TO_M),
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("readyout", 1, DIR_S_TO_M),
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("resp", 1, DIR_S_TO_M),
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]
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class AHBInterface(Record):
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class AHBInterface(Record):
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"""Sets up the AHB interface signals for master and slave."""
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def __init__(self, data_width=32, address_width=32):
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adr_width = 32
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Record.__init__(self, ahb_description(data_width, address_width))
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data_width = 32
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self.data_width = data_width
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addressing = "byte"
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self.address_width = address_width
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master_signals = [
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self.addressing = "byte"
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("addr", adr_width),
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("burst", 3),
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("mastlock", 1),
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("prot", 4),
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("size", 3),
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("trans", 2),
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("wdata", data_width),
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("write", 1),
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("sel", 1),
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]
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slave_signals = [
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("rdata", data_width),
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("readyout", 1),
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("resp", 1),
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]
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def __init__(self):
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Record.__init__(self, set_layout_parameters(self.master_signals + self.slave_signals))
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# AHB to Wishbone ---------------------------------------------------------------------------------
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# AHB to Wishbone ---------------------------------------------------------------------------------
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@ -62,8 +61,8 @@ class AHB2Wishbone(LiteXModule):
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"word" : log2_int(ahb.data_width//8),
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"word" : log2_int(ahb.data_width//8),
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"byte" : 0
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"byte" : 0
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}[wishbone.addressing]
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}[wishbone.addressing]
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assert ahb.data_width == wishbone.data_width
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assert ahb.data_width == wishbone.data_width
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assert ahb.adr_width == wishbone.adr_width + wishbone_adr_shift
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assert ahb.address_width == wishbone.adr_width + wishbone_adr_shift
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# FSM.
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# FSM.
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self.fsm = fsm = FSM()
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self.fsm = fsm = FSM()
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