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Merge pull request #1505 from antmicro/fix-wishbone-arbiter 

Fix Wishbone arbiter
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enjoy-digital 2022-11-15 10:11:59 +01:00 committed by GitHub
parent 4afee8535b 07184d37df
commit 703bd16a96
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1 changed files with 4 additions and 1 deletions
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litex/soc/interconnect/wishbone.py
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@ -166,7 +166,8 @@ class Arbiter(Module):
if controllers is not None:
masters = controllers
self.submodules.rr = roundrobin.RoundRobin(len(masters))
self.submodules.rr = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
cycs = Array(m.cyc for m in masters)
# mux master->slave signals
for name, size, direction in _layout:
@ -185,6 +186,8 @@ class Arbiter(Module):
else:
self.comb += dest.eq(source)
self.comb += self.rr.ce.eq(target.ack | ~cycs[self.rr.grant])
# connect bus requests to round-robin selector
reqs = [m.cyc for m in masters]
self.comb += self.rr.request.eq(Cat(*reqs))