Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

mila: simplify export

Browse source
This commit is contained in:
Florent Kermarrec 2014-10-01 10:06:59 +02:00
parent 111f527647
commit 7043e6a5f3
1 changed files with 6 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
miscope/mila.py
View file

@ -1,10 +1,13 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.fhdl import verilog
from migen.bank.description import * from migen.bank.description import *
from miscope.std import * from miscope.std import *
from miscope.trigger import Trigger from miscope.trigger import Trigger
from miscope.storage import Recorder, RunLengthEncoder from miscope.storage import Recorder, RunLengthEncoder
from mibuild.tools import write_to_file
class MiLa(Module, AutoCSR): class MiLa(Module, AutoCSR):
def __init__(self, width, depth, ports, with_rle=False): def __init__(self, width, depth, ports, with_rle=False):
self.width = width self.width = width
@ -32,7 +35,8 @@ class MiLa(Module, AutoCSR):
else: else:
self.sink.connect(recorder.dat_sink) self.sink.connect(recorder.dat_sink)
def get_csv(self, layout, ns): def export(self, design, layout, filename):
ret, ns = verilog.convert(design, return_ns=True)
r = "" r = ""
def format_line(*args): def format_line(*args):
return ",".join(args) + "\n" return ",".join(args) + "\n"
@ -43,4 +47,4 @@ class MiLa(Module, AutoCSR):
for e in layout: for e in layout:
r += format_line("layout", ns.get_name(e), str(flen(e))) r += format_line("layout", ns.get_name(e), str(flen(e)))
return r write_to_file(filename, r)