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sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit)

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This commit is contained in:
Florent Kermarrec 2015-03-21 21:32:39 +01:00
parent 9bc71f374a
commit 70469e1f37
8 changed files with 29 additions and 50 deletions
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2
misoclib/mem/sdram/__init__.py
View file

@ -9,5 +9,3 @@ def GeomSettings(bank_a, row_a, col_a):
return GeomSettingsT(bank_a, row_a, col_a, max(row_a, col_a))
TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
ControllerSettings = namedtuple("ControllerSettings", "req_queue_size read_time write_time")

12
misoclib/mem/sdram/core/__init__.py
View file

@ -1,3 +1,5 @@
from collections import namedtuple
from migen.fhdl.std import *
from migen.genlib.record import *
from migen.bank.description import *
@ -6,15 +8,17 @@ from misoclib.mem.sdram.phy import dfii
from misoclib.mem.sdram.core import minicon, lasmicon
from misoclib.mem.sdram.core import lasmixbar
ControllerSettings = namedtuple("ControllerSettings", "type req_queue_size read_time write_time")
class SDRAMCore(Module, AutoCSR):
def __init__(self, phy, ramcon_type, geom_settings, timing_settings, controller_settings, **kwargs):
def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs):
# DFI
self.submodules.dfii = dfii.DFIInjector(geom_settings.mux_a, geom_settings.bank_a,
phy.settings.dfi_d, phy.settings.nphases)
self.comb += Record.connect(self.dfii.master, phy.dfi)
# LASMICON
if ramcon_type == "lasmicon":
if controller_settings.type == "lasmicon":
self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, geom_settings, timing_settings,
controller_settings, **kwargs)
self.comb += Record.connect(controller.dfi, self.dfii.slave)
@ -22,8 +26,8 @@ class SDRAMCore(Module, AutoCSR):
self.submodules.crossbar = crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits)
# MINICON
elif ramcon_type == "minicon":
elif controller_settings.type == "minicon":
self.submodules.controller = controller = minicon.Minicon(phy.settings, geom_settings, timing_settings)
self.comb += Record.connect(controller.dfi, self.dfii.slave)
else:
raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type))
raise ValueError("Unsupported SDRAM controller type: {}".format(controller_settings.type))

24
misoclib/soc/sdram.py
View file

@ -2,7 +2,7 @@ from migen.fhdl.std import *
from migen.bus import wishbone, csr
from migen.genlib.record import *
from misoclib.mem.sdram.core import SDRAMCore
from misoclib.mem.sdram.core import ControllerSettings, SDRAMCore
from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
from misoclib.soc import SoC, mem_decoder
@ -16,13 +16,21 @@ class SDRAMSoC(SoC):
csr_map.update(SoC.csr_map)
def __init__(self, platform, clk_freq,
ramcon_type="lasmicon",
sdram_controller_type="lasmicon", sdram_controller_req_queue_size=8,
sdram_controller_read_time=32, sdram_controller_write_time=16,
with_l2=True, l2_size=8192,
with_bandwidth=False, # specific to LASMICON,
with_memtest=False, # ignored for MINICON
**kwargs):
SoC.__init__(self, platform, clk_freq, **kwargs)
self.ramcon_type = ramcon_type
self.sdram_controller_type = sdram_controller_type
self.sdram_controller_settings = ControllerSettings(
type=sdram_controller_type,
# Below parameters are only used by LASMIcon
req_queue_size=sdram_controller_req_queue_size,
read_time=sdram_controller_read_time,
write_time=sdram_controller_write_time
)
self.with_l2 = with_l2
self.l2_size = l2_size
@ -32,18 +40,18 @@ class SDRAMSoC(SoC):
self._sdram_phy_registered = False
def register_sdram_phy(self, phy, geom_settings, timing_settings, controller_settings):
def register_sdram_phy(self, phy, geom_settings, timing_settings):
if self._sdram_phy_registered:
raise FinalizeError
self._sdram_phy_registered = True
if self.ramcon_type == "minicon" and phy.settings.memtype != "SDR":
if self.sdram_controller_type == "minicon" and phy.settings.memtype != "SDR":
raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")")
# Core
self.submodules.sdram = SDRAMCore(phy, self.ramcon_type, geom_settings, timing_settings, controller_settings)
self.submodules.sdram = SDRAMCore(phy, geom_settings, timing_settings, self.sdram_controller_settings)
# LASMICON frontend
if self.ramcon_type == "lasmicon":
if self.sdram_controller_type == "lasmicon":
if self.with_bandwidth:
self.sdram.controller.multiplexer.add_bandwidth()
@ -66,7 +74,7 @@ class SDRAMSoC(SoC):
self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size)
# MINICON frontend
elif self.ramcon_type == "minicon":
elif self.sdram_controller_type == "minicon":
sdram_width = flen(self.sdram.controller.bus.dat_r)
main_ram_size = 2**(geom_settings.bank_a+geom_settings.row_a+geom_settings.col_a)*sdram_width//8

8
targets/de0nano.py
View file

@ -92,13 +92,7 @@ class BaseSoC(SDRAMSoC):
if not self.with_integrated_main_ram:
sdram_module = IS42S16160(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings,
sdram_controller_settings)
self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
default_subtarget = BaseSoC

8
targets/kc705.py
View file

@ -85,14 +85,8 @@ class BaseSoC(SDRAMSoC):
if not self.with_integrated_main_ram:
sdram_modules = MT8JTF12864(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings,
sdram_controller_settings)
self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings)
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()

9
targets/mlabs_video.py
View file

@ -43,16 +43,9 @@ class BaseSoC(SDRAMSoC):
if not self.with_integrated_main_ram:
sdram_modules = MT46V32M16(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings,
sdram_controller_settings)
self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),

8
targets/pipistrello.py
View file

@ -100,11 +100,6 @@ class BaseSoC(SDRAMSoC):
if not self.with_integrated_main_ram:
sdram_module = MT46H32M16(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"),
"LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
self.comb += [
@ -114,8 +109,7 @@ class BaseSoC(SDRAMSoC):
platform.add_platform_command("""
PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
""")
self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings,
sdram_controller_settings)
self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
# If not in ROM, BIOS is in SPI flash

8
targets/ppro.py
View file

@ -76,14 +76,8 @@ class BaseSoC(SDRAMSoC):
if not self.with_integrated_main_ram:
sdram_module = MT48LC4M16(clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings,
sdram_controller_settings)
self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000