corelogic/roundrobin: fix request width (again)

2012-11-29 23:47:51 +01:00 · 2012-11-29 23:47:51 +01:00 · 7093939309
parent 31c722f993
commit 7093939309
1 changed files with 1 additions and 1 deletions
--- a/migen/corelogic/roundrobin.py
+++ b/migen/corelogic/roundrobin.py
@ -5,7 +5,7 @@ from migen.fhdl.structure import *
 class RoundRobin:
 	def __init__(self, n, switch_policy=SP_WITHDRAW):
 		self.n = n
-		self.request = Signal(nbits=self.n)
+		self.request = Signal(self.n)
 		self.grant = Signal(max=self.n)
 		self.switch_policy = switch_policy
 		if self.switch_policy == SP_CE: