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corelogic/roundrobin: fix request width (again)

This commit is contained in:
Sebastien Bourdeauducq 2012-11-29 23:47:51 +01:00
parent 31c722f993
commit 7093939309
1 changed files with 1 additions and 1 deletions
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2
migen/corelogic/roundrobin.py
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@ -5,7 +5,7 @@ from migen.fhdl.structure import *
class RoundRobin: class RoundRobin:
def __init__(self, n, switch_policy=SP_WITHDRAW): def __init__(self, n, switch_policy=SP_WITHDRAW):
self.n = n self.n = n
self.request = Signal(nbits=self.n) self.request = Signal(self.n)
self.grant = Signal(max=self.n) self.grant = Signal(max=self.n)
self.switch_policy = switch_policy self.switch_policy = switch_policy
if self.switch_policy == SP_CE: if self.switch_policy == SP_CE: