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sim/verilator: add multithread support (default=1)

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Florent Kermarrec 2018-09-24 12:43:29 +02:00
parent 7f0d116d88
commit 70a32ed86f
3 changed files with 11 additions and 8 deletions
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6
litex/boards/targets/sim.py
View file

@ -144,6 +144,8 @@ def main():
parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation") parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
parser.add_argument("--threads", default=1,
help="set number of threads (default=1)")
parser.add_argument("--rom-init", default=None, parser.add_argument("--rom-init", default=None,
help="rom_init file") help="rom_init file")
parser.add_argument("--ram-init", default=None, parser.add_argument("--ram-init", default=None,
@ -183,10 +185,10 @@ def main():
**soc_kwargs) **soc_kwargs)
builder_kwargs["csr_csv"] = "csr.csv" builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs) builder = Builder(soc, **builder_kwargs)
vns = builder.build(run=False, sim_config=sim_config) vns = builder.build(run=False, threads=args.threads, sim_config=sim_config)
if args.with_analyzer: if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv") soc.analyzer.export_csv(vns, "analyzer.csv")
builder.build(build=False, sim_config=sim_config) builder.build(build=False, threads=args.threads, sim_config=sim_config)
if __name__ == "__main__": if __name__ == "__main__":

1
litex/build/sim/core/Makefile
View file

@ -27,6 +27,7 @@ sim: mkdir $(OBJS_SIM)
verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \ verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \
$(SRCS_SIM_CPP) $(OBJS_SIM) \ $(SRCS_SIM_CPP) $(OBJS_SIM) \
--top-module dut \ --top-module dut \
--threads $(THREADS) \
-CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \ -CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
-LDFLAGS "$(LDFLAGS)" \ -LDFLAGS "$(LDFLAGS)" \
-trace $(INC_DIR) -trace $(INC_DIR)

12
litex/build/sim/verilator.py
View file

@ -103,13 +103,13 @@ def _generate_sim_config(config):
tools.write_to_file("sim_config.js", content) tools.write_to_file("sim_config.js", content)
def _build_sim(platform, build_name, verbose): def _build_sim(platform, build_name, threads, verbose):
makefile = os.path.join(core_directory, 'Makefile') makefile = os.path.join(core_directory, 'Makefile')
build_script_contents = """\ build_script_contents = """\
rm -rf obj_dir/ rm -rf obj_dir/
make -C . -f {} make -C . -f {} THREADS={}
mkdir -p modules && cp obj_dir/*.so modules mkdir -p modules && cp obj_dir/*.so modules
""".format(makefile) """.format(makefile, threads)
build_script_file = "build_" + build_name + ".sh" build_script_file = "build_" + build_name + ".sh"
tools.write_to_file(build_script_file, build_script_contents, force_unix=True) tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
@ -145,8 +145,8 @@ def _run_sim(build_name, as_root=False):
class SimVerilatorToolchain: class SimVerilatorToolchain:
def build(self, platform, fragment, build_dir="build", build_name="dut", def build(self, platform, fragment, build_dir="build", build_name="dut",
toolchain_path=None, serial="console", build=True, run=True, verbose=True, toolchain_path=None, serial="console", build=True, run=True, threads=1,
sim_config=None): verbose=True, sim_config=None):
os.makedirs(build_dir, exist_ok=True) os.makedirs(build_dir, exist_ok=True)
os.chdir(build_dir) os.chdir(build_dir)
@ -173,7 +173,7 @@ class SimVerilatorToolchain:
if sim_config: if sim_config:
_generate_sim_config(sim_config) _generate_sim_config(sim_config)
_build_sim(platform, build_name, verbose) _build_sim(platform, build_name, threads, verbose)
if run: if run:
_run_sim(build_name, as_root=sim_config.has_module("ethernet")) _run_sim(build_name, as_root=sim_config.has_module("ethernet"))