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https://github.com/enjoy-digital/litex.git
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integration/soc: add software_debug parameter to add_ethernet, add_(spi)sdcard to ease enabling software debug traces from design.
This commit is contained in:
parent
c7056b77bb
commit
70d364cf4e
4 changed files with 28 additions and 11 deletions
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@ -1328,16 +1328,17 @@ class LiteXSoC(SoC):
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base_address = self.bus.regions["main_ram"].origin)
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base_address = self.bus.regions["main_ram"].origin)
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# Add Ethernet ---------------------------------------------------------------------------------
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# Add Ethernet ---------------------------------------------------------------------------------
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def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth"):
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def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", software_debug=False):
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# Imports
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# Imports
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from liteeth.mac import LiteEthMAC
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from liteeth.mac import LiteEthMAC
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# MAC
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# MAC
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ethmac = LiteEthMAC(
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ethmac = LiteEthMAC(
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phy = phy,
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phy = phy,
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dw = 32,
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dw = 32,
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interface = "wishbone",
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interface = "wishbone",
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endianness = self.cpu.endianness)
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endianness = self.cpu.endianness,
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with_preamble_crc = not software_debug)
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ethmac = ClockDomainsRenamer({
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ethmac = ClockDomainsRenamer({
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"eth_tx": phy_cd + "_tx",
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"eth_tx": phy_cd + "_tx",
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"eth_rx": phy_cd + "_rx"})(ethmac)
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"eth_rx": phy_cd + "_rx"})(ethmac)
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@ -1347,6 +1348,7 @@ class LiteXSoC(SoC):
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self.csr.add(name, use_loc_if_exists=True)
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self.csr.add(name, use_loc_if_exists=True)
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if self.irq.enabled:
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if self.irq.enabled:
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self.irq.add(name, use_loc_if_exists=True)
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self.irq.add(name, use_loc_if_exists=True)
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# Timing constraints
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# Timing constraints
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if hasattr(phy, "crg"):
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if hasattr(phy, "crg"):
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eth_rx_clk = phy.crg.cd_eth_rx.clk
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eth_rx_clk = phy.crg.cd_eth_rx.clk
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@ -1361,6 +1363,11 @@ class LiteXSoC(SoC):
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eth_rx_clk,
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eth_rx_clk,
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eth_tx_clk)
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eth_tx_clk)
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# Software Debug
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if software_debug:
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self.add_constant("ETH_UDP_TX_DEBUG")
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self.add_constant("ETH_UDP_RX_DEBUG")
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# Add Etherbone --------------------------------------------------------------------------------
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# Add Etherbone --------------------------------------------------------------------------------
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def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth",
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def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth",
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mac_address = 0x10e2d5000000,
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mac_address = 0x10e2d5000000,
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@ -1425,7 +1432,7 @@ class LiteXSoC(SoC):
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self.csr.add(name, use_loc_if_exists=True)
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self.csr.add(name, use_loc_if_exists=True)
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# Add SPI SDCard -------------------------------------------------------------------------------
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# Add SPI SDCard -------------------------------------------------------------------------------
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def add_spi_sdcard(self, name="spisdcard", spi_clk_freq=400e3):
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def add_spi_sdcard(self, name="spisdcard", spi_clk_freq=400e3, software_debug=False):
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pads = self.platform.request(name)
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pads = self.platform.request(name)
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if hasattr(pads, "rst"):
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if hasattr(pads, "rst"):
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self.comb += pads.rst.eq(0)
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self.comb += pads.rst.eq(0)
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@ -1434,8 +1441,11 @@ class LiteXSoC(SoC):
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setattr(self.submodules, name, spisdcard)
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setattr(self.submodules, name, spisdcard)
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self.csr.add(name, use_loc_if_exists=True)
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self.csr.add(name, use_loc_if_exists=True)
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if software_debug:
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self.add_constant("SPISDCARD_DEBUG")
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# Add SDCard -----------------------------------------------------------------------------------
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# Add SDCard -----------------------------------------------------------------------------------
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def add_sdcard(self, name="sdcard", mode="read+write", use_emulator=False):
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def add_sdcard(self, name="sdcard", mode="read+write", use_emulator=False, software_debug=False):
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assert mode in ["read", "write", "read+write"]
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assert mode in ["read", "write", "read+write"]
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# Imports
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# Imports
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from litesdcard.emulator import SDEmulator
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from litesdcard.emulator import SDEmulator
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@ -1488,6 +1498,10 @@ class LiteXSoC(SoC):
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self.sdirq.mem2block_dma.trigger.eq(self.sdmem2block.irq),
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self.sdirq.mem2block_dma.trigger.eq(self.sdmem2block.irq),
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]
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]
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# Software Debug
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if software_debug:
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self.add_constant("SDCARD_DEBUG")
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# Add SATA -------------------------------------------------------------------------------------
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# Add SATA -------------------------------------------------------------------------------------
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def add_sata(self, name="sata", phy=None, mode="read+write"):
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def add_sata(self, name="sata", phy=None, mode="read+write"):
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# Imports
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# Imports
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@ -7,6 +7,7 @@
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#include <generated/csr.h>
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#include <generated/csr.h>
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#include <generated/mem.h>
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#include <generated/mem.h>
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#include <generated/soc.h>
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#ifdef CSR_ETHMAC_BASE
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#ifdef CSR_ETHMAC_BASE
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@ -17,8 +18,8 @@
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#include "udp.h"
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#include "udp.h"
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//#define DEBUG_UDP_TX
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//#define ETH_UDP_TX_DEBUG
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//#define DEBUG_UDP_RX
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//#define ETH_UDP_RX_DEBUG
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#define ETHERTYPE_ARP 0x0806
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#define ETHERTYPE_ARP 0x0806
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#define ETHERTYPE_IP 0x0800
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#define ETHERTYPE_IP 0x0800
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@ -144,7 +145,7 @@ static void send_packet(void)
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txlen += 4;
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txlen += 4;
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#endif
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#endif
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#ifdef DEBUG_LITEETH_UDP_TX
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#ifdef ETH_UDP_TX_DEBUG
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int j;
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int j;
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printf(">>>> txlen : %d\n", txlen);
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printf(">>>> txlen : %d\n", txlen);
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for(j=0;j<txlen;j++)
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for(j=0;j<txlen;j++)
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@ -381,7 +382,7 @@ static void process_frame(void)
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{
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{
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flush_cpu_dcache();
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flush_cpu_dcache();
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#ifdef DEBUG_LITEETH_UDP_RX
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#ifdef ETH_UDP_RX_DEBUG
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int j;
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int j;
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printf("<<< rxlen : %d\n", rxlen);
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printf("<<< rxlen : %d\n", rxlen);
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for(j=0;j<rxlen;j++)
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for(j=0;j<rxlen;j++)
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@ -11,6 +11,7 @@
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#include <generated/csr.h>
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#include <generated/csr.h>
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#include <generated/mem.h>
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#include <generated/mem.h>
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#include <generated/soc.h>
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#include <system.h>
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#include <system.h>
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#include <libfatfs/ff.h>
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#include <libfatfs/ff.h>
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@ -10,6 +10,7 @@
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#include <generated/csr.h>
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#include <generated/csr.h>
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#include <generated/mem.h>
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#include <generated/mem.h>
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#include <generated/soc.h>
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#include <system.h>
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#include <system.h>
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#include <libfatfs/ff.h>
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#include <libfatfs/ff.h>
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