integration/soc: add software_debug parameter to add_ethernet, add_(spi)sdcard to ease enabling software debug traces from design.

litex/soc/integration/soc.py

@@ -1328,7 +1328,7 @@ class LiteXSoC(SoC):
                 base_address = self.bus.regions["main_ram"].origin)
 
     # Add Ethernet ---------------------------------------------------------------------------------
-    def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth"):
+    def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", software_debug=False):
         # Imports
         from liteeth.mac import LiteEthMAC
 
@@ -1337,7 +1337,8 @@ class LiteXSoC(SoC):
             phy               = phy,
             dw                = 32,
             interface         = "wishbone",
-            endianness = self.cpu.endianness)
+            endianness        = self.cpu.endianness,
+            with_preamble_crc = not software_debug)
         ethmac = ClockDomainsRenamer({
             "eth_tx": phy_cd + "_tx",
             "eth_rx": phy_cd + "_rx"})(ethmac)
@@ -1347,6 +1348,7 @@ class LiteXSoC(SoC):
         self.csr.add(name, use_loc_if_exists=True)
         if self.irq.enabled:
             self.irq.add(name, use_loc_if_exists=True)
+
         # Timing constraints
         if hasattr(phy, "crg"):
             eth_rx_clk = phy.crg.cd_eth_rx.clk
@@ -1361,6 +1363,11 @@ class LiteXSoC(SoC):
             eth_rx_clk,
             eth_tx_clk)
 
+        # Software Debug
+        if software_debug:
+            self.add_constant("ETH_UDP_TX_DEBUG")
+            self.add_constant("ETH_UDP_RX_DEBUG")
+
     # Add Etherbone --------------------------------------------------------------------------------
     def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth",
         mac_address  = 0x10e2d5000000,
@@ -1425,7 +1432,7 @@ class LiteXSoC(SoC):
         self.csr.add(name, use_loc_if_exists=True)
 
     # Add SPI SDCard -------------------------------------------------------------------------------
-    def add_spi_sdcard(self, name="spisdcard", spi_clk_freq=400e3):
+    def add_spi_sdcard(self, name="spisdcard", spi_clk_freq=400e3, software_debug=False):
         pads = self.platform.request(name)
         if hasattr(pads, "rst"):
             self.comb += pads.rst.eq(0)
@@ -1434,8 +1441,11 @@ class LiteXSoC(SoC):
         setattr(self.submodules, name, spisdcard)
         self.csr.add(name, use_loc_if_exists=True)
 
+        if software_debug:
+            self.add_constant("SPISDCARD_DEBUG")
+
     # Add SDCard -----------------------------------------------------------------------------------
-    def add_sdcard(self, name="sdcard", mode="read+write", use_emulator=False):
+    def add_sdcard(self, name="sdcard", mode="read+write", use_emulator=False, software_debug=False):
         assert mode in ["read", "write", "read+write"]
         # Imports
         from litesdcard.emulator import SDEmulator
@@ -1488,6 +1498,10 @@ class LiteXSoC(SoC):
             self.sdirq.mem2block_dma.trigger.eq(self.sdmem2block.irq),
         ]
 
+        # Software Debug
+        if software_debug:
+            self.add_constant("SDCARD_DEBUG")
+
     # Add SATA -------------------------------------------------------------------------------------
     def add_sata(self, name="sata", phy=None, mode="read+write"):
         # Imports

litex/soc/software/libliteeth/udp.c

@@ -7,6 +7,7 @@
 
 #include <generated/csr.h>
 #include <generated/mem.h>
+#include <generated/soc.h>
 
 #ifdef CSR_ETHMAC_BASE
 
@@ -17,8 +18,8 @@
 
 #include "udp.h"
 
-//#define DEBUG_UDP_TX
-//#define DEBUG_UDP_RX
+//#define ETH_UDP_TX_DEBUG
+//#define ETH_UDP_RX_DEBUG
 
 #define ETHERTYPE_ARP 0x0806
 #define ETHERTYPE_IP  0x0800
@@ -144,7 +145,7 @@ static void send_packet(void)
 	txlen += 4;
 #endif
 
-#ifdef DEBUG_LITEETH_UDP_TX
+#ifdef ETH_UDP_TX_DEBUG
 	int j;
 	printf(">>>> txlen : %d\n", txlen);
 	for(j=0;j<txlen;j++)
@@ -381,7 +382,7 @@ static void process_frame(void)
 {
 	flush_cpu_dcache();
 
-#ifdef DEBUG_LITEETH_UDP_RX
+#ifdef ETH_UDP_RX_DEBUG
 	int j;
 	printf("<<< rxlen : %d\n", rxlen);
 	for(j=0;j<rxlen;j++)

litex/soc/software/liblitesdcard/sdcard.c

@@ -11,6 +11,7 @@
 
 #include <generated/csr.h>
 #include <generated/mem.h>
+#include <generated/soc.h>
 #include <system.h>
 
 #include <libfatfs/ff.h>

litex/soc/software/liblitesdcard/spisdcard.c

@@ -10,6 +10,7 @@
 
 #include <generated/csr.h>
 #include <generated/mem.h>
+#include <generated/soc.h>
 #include <system.h>
 
 #include <libfatfs/ff.h>