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interconnect/wishbone: increase WB address width to 31

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This is needed to support memory regions up to 4GB in size (currently
limited to 2GB, or 0x8000_0000).

FIXME: CI complains about assertions re. axi_lite.address_width in
       relationship to len(wishbone.adr) and wishbone_adr_shift, which
       seems to be a problem on the 32bit (vexriscv?) CPU used for CI,
       but seems to work fine on Rocket.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

foo
This commit is contained in:
Gabriel Somlo 2020-08-03 14:32:26 -04:00
parent b8c9da81ea
commit 70eae5cbf9
1 changed files with 1 additions and 1 deletions
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2
litex/soc/interconnect/wishbone.py
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@ -35,7 +35,7 @@ _layout = [
class Interface(Record):
def __init__(self, data_width=32, adr_width=30):
def __init__(self, data_width=32, adr_width=31):
self.data_width = data_width
self.adr_width = adr_width
Record.__init__(self, set_layout_parameters(_layout,