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m1crg: advance off-chip DDR clock phase

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This commit is contained in:
Sebastien Bourdeauducq 2013-02-24 17:41:56 +01:00
parent 5e6505b946
commit 70f4c74d46
1 changed files with 25 additions and 11 deletions
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36
verilog/m1crg/m1crg.v
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@ -101,6 +101,7 @@ wire pllout1;
wire pllout2; wire pllout2;
wire pllout3; wire pllout3;
wire pllout4; wire pllout4;
wire pllout5;
PLL_ADV #( PLL_ADV #(
.BANDWIDTH("OPTIMIZED"), .BANDWIDTH("OPTIMIZED"),
@ -108,24 +109,31 @@ PLL_ADV #(
.CLKFBOUT_PHASE(0.0), .CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(in_period), .CLKIN1_PERIOD(in_period),
.CLKIN2_PERIOD(in_period), .CLKIN2_PERIOD(in_period),
.CLKOUT0_DIVIDE(f_div), .CLKOUT0_DIVIDE(f_div),
.CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0), .CLKOUT0_PHASE(0.0),
.CLKOUT1_DIVIDE(f_div), .CLKOUT1_DIVIDE(f_div),
.CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0), .CLKOUT1_PHASE(0.0),
.CLKOUT2_DIVIDE(2*f_div), .CLKOUT2_DIVIDE(2*f_div),
.CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(270.0), .CLKOUT2_PHASE(270.0),
.CLKOUT3_DIVIDE(4*f_div), .CLKOUT3_DIVIDE(4*f_div),
.CLKOUT3_DUTY_CYCLE(0.5), .CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0.0), .CLKOUT3_PHASE(0.0),
.CLKOUT4_DIVIDE(4*f_mult), .CLKOUT4_DIVIDE(4*f_mult),
.CLKOUT4_DUTY_CYCLE(0.5), .CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0), .CLKOUT4_PHASE(0.0),
.CLKOUT5_DIVIDE(7),
.CLKOUT5_DIVIDE(2*f_div),
.CLKOUT5_DUTY_CYCLE(0.5), .CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0.0), .CLKOUT5_PHASE(250.0),
.COMPENSATION("INTERNAL"), .COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(1), .DIVCLK_DIVIDE(1),
.REF_JITTER(0.100), .REF_JITTER(0.100),
@ -136,10 +144,10 @@ PLL_ADV #(
.CLKFBOUT(buf_pll_fb_out), .CLKFBOUT(buf_pll_fb_out),
.CLKOUT0(pllout0), /* < x4 clock for writes */ .CLKOUT0(pllout0), /* < x4 clock for writes */
.CLKOUT1(pllout1), /* < x4 clock for reads */ .CLKOUT1(pllout1), /* < x4 clock for reads */
.CLKOUT2(pllout2), /* < x2 90 clock to generate memory clock, clock DQS and memory address and control signals. */ .CLKOUT2(pllout2), /* < x2 270 clock for DQS, memory address and control signals */
.CLKOUT3(pllout3), /* < x1 clock for system and memory controller */ .CLKOUT3(pllout3), /* < x1 clock for system and memory controller */
.CLKOUT4(pllout4), /* < buffered clk50 */ .CLKOUT4(pllout4), /* < buffered clk50 */
.CLKOUT5(), .CLKOUT5(pllout5), /* < x2 clock to off-chip DDR */
.CLKOUTDCM0(), .CLKOUTDCM0(),
.CLKOUTDCM1(), .CLKOUTDCM1(),
.CLKOUTDCM2(), .CLKOUTDCM2(),
@ -194,6 +202,12 @@ BUFG bufg_x1(
.O(sys_clk) .O(sys_clk)
); );
wire clk2x_off;
BUFG bufg_x2_offclk(
.I(pllout5),
.O(clk2x_off)
);
/* /*
* SDRAM clock * SDRAM clock
@ -205,8 +219,8 @@ ODDR2 #(
.SRTYPE("SYNC") .SRTYPE("SYNC")
) sd_clk_forward_p ( ) sd_clk_forward_p (
.Q(ddr_clk_pad_p), .Q(ddr_clk_pad_p),
.C0(clk2x_270), .C0(clk2x_off),
.C1(~clk2x_270), .C1(~clk2x_off),
.CE(1'b1), .CE(1'b1),
.D0(1'b1), .D0(1'b1),
.D1(1'b0), .D1(1'b0),
@ -219,8 +233,8 @@ ODDR2 #(
.SRTYPE("SYNC") .SRTYPE("SYNC")
) sd_clk_forward_n ( ) sd_clk_forward_n (
.Q(ddr_clk_pad_n), .Q(ddr_clk_pad_n),
.C0(clk2x_270), .C0(clk2x_off),
.C1(~clk2x_270), .C1(~clk2x_off),
.CE(1'b1), .CE(1'b1),
.D0(1'b0), .D0(1'b0),
.D1(1'b1), .D1(1'b1),