cores/spi/spi_bone: Separate SPI IOs handling from Signals.

litex/soc/cores/spi/spi_bone.py

@@ -149,23 +149,14 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
             2 : SPI2WireDocumentation(),
         }[wires]
 
-
+        # SPI IOs.
-        # Signals.
+        # -------
-        # --------
         clk     = Signal()
         cs_n    = Signal()
         mosi    = Signal()
         miso    = Signal()
         miso_en = Signal()
 
-        counter      = Signal(8)
-        write_offset = Signal(5)
-        command      = Signal(8)
-        address      = Signal(32)
-        value        = Signal(32)
-        wr           = Signal()
-        sync_byte    = Signal(8)
-
         self.specials += MultiReg(pads.clk, clk)
         if wires in [2, 3]:
             io = TSTriple()
@@ -183,6 +174,16 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
             else:
                 self.comb += pads.miso.eq(miso)
 
+        # Signals.
+        # --------
+        counter      = Signal(8)
+        write_offset = Signal(5)
+        command      = Signal(8)
+        address      = Signal(32)
+        value        = Signal(32)
+        wr           = Signal()
+        sync_byte    = Signal(8)
+
         clk_last    = Signal()
         clk_rising  = Signal()
         clk_falling = Signal()