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targets/mlabs_video: rename sdram_module to sdram_modules to reflect that we have 2 modules sharing the same characteristics

This commit is contained in:
Florent Kermarrec 2015-03-21 18:10:56 +01:00
parent 1c0e306176
commit 711540e15c
1 changed files with 2 additions and 2 deletions
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4
targets/mlabs_video.py
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@ -42,7 +42,7 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq) self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
if not self.with_main_ram: if not self.with_main_ram:
sdram_module = MT46V32M16(self.clk_freq) sdram_modules = MT46V32M16(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings( sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8, req_queue_size=8,
read_time=32, read_time=32,
@ -50,7 +50,7 @@ class BaseSoC(SDRAMSoC):
) )
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1") rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings,
sdram_controller_settings) sdram_controller_settings)