Merge pull request #1496 from MateuszKarlic/json2renode-update
json2renode: Multicore configuration support
This commit is contained in:
enjoy-digital
GitHub
commit
7157b4c5e8
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@ -1,6 +1,6 @@
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#!/usr/bin/env python3
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"""
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Copyright (c) 2019-2021 Antmicro <www.antmicro.com>
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Copyright (c) 2019-2022 Antmicro <www.antmicro.com>
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Renode platform definition (repl) and script (resc) generator for LiteX SoC.
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@ -20,6 +20,14 @@ import argparse
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# and should not be generated automatically
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non_generated_mem_regions = ['ethmac', 'csr']
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def get_soc_interrupt_parent(csr):
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'''
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We assume that for multi-core setups plic will be used hence cpu0 is enough
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'''
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if 'plic' in csr['memories']:
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return 'plic'
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else:
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return 'cpu0'
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def get_descriptor(csr, name, size=None):
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res = { 'base': csr['csr_bases'][name], 'constants': {} }
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@ -110,7 +118,8 @@ ethmac: Network.LiteX_Ethernet{} @ {{
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interrupt_name = '{}_interrupt'.format(name)
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if interrupt_name in csr['constants']:
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result += ' -> cpu@{}\n'.format(
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result += ' -> {}@{}\n'.format(
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get_soc_interrupt_parent(csr),
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csr['constants'][interrupt_name])
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result += """
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@ -204,8 +213,54 @@ def get_cpu_type(csr):
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return (kind, variant)
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def get_cpu_count(csr):
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return csr['constants']['config_cpu_count']
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def generate_cpu(csr, time_provider):
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vexriscv_common_kind = {
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'name': 'VexRiscv',
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'variants': {
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'linux': {
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'properties': ['cpuType: "rv32ima"', 'privilegeArchitecture: PrivilegeArchitecture.Priv1_10'],
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},
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'i': {
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'properties': ['cpuType: "rv32i"'],
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},
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'im': {
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'properties': ['cpuType: "rv32im"'],
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},
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'ima': {
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'properties': ['cpuType: "rv32ima"'],
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},
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'imac': {
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'properties': ['cpuType: "rv32imac"'],
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},
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'others': {
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'properties': ['cpuType: "rv32im"'],
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}
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},
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'supports_time_provider': True,
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}
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cpu_kinds = {
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'vexriscv': vexriscv_common_kind,
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'vexriscv_smp': vexriscv_common_kind,
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'picorv32': {
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'name': 'PicoRV32',
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'properties': ['cpuType: "rv32imc"'],
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},
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'minerva': {
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'name': 'Minerva',
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},
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'ibex': {
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'name': 'IbexRiscV32',
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},
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'cv32e40p': {
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'name': 'CV32E40P',
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'supports_time_provider': True,
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'properties': ['cpuType: "rv32imc"'],
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}
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}
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def generate_cpu(csr, time_provider, number_of_cores):
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""" Generates definition of a CPU.
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Returns:
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@ -213,63 +268,39 @@ def generate_cpu(csr, time_provider):
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"""
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kind, variant = get_cpu_type(csr)
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if kind == 'vexriscv' or kind == 'vexriscv_smp':
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result = """
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cpu: CPU.VexRiscv @ sysbus
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"""
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if variant == 'linux':
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result += """
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cpuType: "rv32ima"
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privilegeArchitecture: PrivilegeArchitecture.Priv1_10
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"""
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elif variant in ["i", "im", "ima", "imac"]:
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result += """
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cpuType: "rv32{}"
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""".format(variant)
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else:
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result += """
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cpuType: "rv32im"
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"""
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if time_provider:
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result += """
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timeProvider: {}
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""".format(time_provider)
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try:
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cpu = cpu_kinds[kind]
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return result
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elif kind == 'picorv32':
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return """
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cpu: CPU.PicoRV32 @ sysbus
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cpuType: "rv32imc"
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"""
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elif kind == 'minerva':
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return """
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cpu: CPU.Minerva @ sysbus
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"""
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elif kind == 'ibex':
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return """
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cpu: CPU.IbexRiscV32 @ sysbus
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"""
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elif kind == 'cv32e40p':
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result = """
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cpu: CPU.CV32E40P @ sysbus
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"""
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if variant == 'standard':
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result += """
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cpuType: "rv32imc"
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"""
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else:
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result += """
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cpuType: "rv32imc"
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"""
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if time_provider:
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result += """
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timeProvider: {}
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""".format(time_provider)
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cpu_string = f'{cpu["name"]} @ sysbus\n'
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def unpack_properties(prop_list):
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return ''.join([f' {prop}\n' for prop in prop_list])
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return result
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else:
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raise Exception('Unsupported cpu type: {}'.format(kind))
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if 'properties' in cpu:
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cpu_string += unpack_properties(cpu["properties"])
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if 'variants' in cpu:
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variant = cpu['variants'].get(variant)
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if variant is None:
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variant = cpu['variants'].get('others', [])
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if 'properties' in variant:
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cpu_string += unpack_properties(variant["properties"])
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except KeyError:
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raise Exception(f'Unsupported cpu type: {kind}')
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result = ''
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for cpu_id in range(0, number_of_cores):
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result += f"""
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cpu{cpu_id}: CPU.{cpu_string.strip()}
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hartId: {cpu_id}
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"""
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if cpu.get('supports_time_provider', False):
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result += f' timeProvider: {time_provider}\n'
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return result
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def generate_peripheral(csr, name, **kwargs):
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""" Generates definition of a peripheral.
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@ -298,7 +329,7 @@ def generate_peripheral(csr, name, **kwargs):
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for constant, val in peripheral['constants'].items():
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if 'ignored_constants' not in kwargs or constant not in kwargs['ignored_constants']:
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if constant == 'interrupt':
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result += ' -> cpu@{}\n'.format(val)
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result += ' -> {}@{}\n'.format(get_soc_interrupt_parent(csr), val)
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else:
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result += ' {}: {}\n'.format(constant, val)
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@ -413,31 +444,37 @@ mmc_controller: SD.LiteSDCard{} @ {{
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return result
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def generate_clint(clint, frequency):
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def generate_clint(clint, frequency, number_of_cores):
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# TODO: this is configuration for VexRiscv - add support for other CPU types
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result = """
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clint: IRQControllers.CoreLevelInterruptor @ {}
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frequency: {}
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[0, 1] -> cpu@[101, 100]
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numberOfTargets: {}
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""".format(generate_sysbus_registration(clint,
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skip_braces=True,
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skip_size=True),
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frequency)
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frequency, number_of_cores)
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for cpu_id in range(0, number_of_cores):
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result += f" [{2 * cpu_id}, {2 * cpu_id + 1}] -> cpu{cpu_id}@[101, 100]\n"
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return result
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def generate_plic(plic):
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def generate_plic(plic, number_of_cores):
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# TODO: this is configuration for linux-on-litex-vexriscv - add support for other CPU types
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result = """
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plic: IRQControllers.PlatformLevelInterruptController @ {}
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[0, 1] -> cpu@[11, 9]
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numberOfSources: 31
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numberOfContexts: 2
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numberOfContexts: {}
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prioritiesEnabled: false
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""".format(generate_sysbus_registration(plic,
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skip_braces=True,
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skip_size=True))
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skip_size=True),
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2 * number_of_cores)
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for cpu_id in range(0, number_of_cores):
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result += f" [{2 * cpu_id}, {2 * cpu_id + 1}] -> cpu{cpu_id}@[11, 9]\n"
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return result
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@ -489,6 +526,67 @@ def get_clock_frequency(csr):
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# has different names
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return csr['constants']['config_clock_frequency' if 'config_clock_frequency' in csr['constants'] else 'system_clock_frequency']
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def generate_gpio_port(csr, name, **kwargs):
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peripheral = get_descriptor(csr, name)
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ints = ''
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if 'interrupt' in kwargs:
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ints += f' IRQ -> {get_soc_interrupt_parent(csr)}@{kwargs["interrupt"]}'
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if 'connections' in kwargs:
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for irq, target in zip(kwargs['connections'], kwargs['connections_targets']):
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ints += f' {irq} -> {target}\n'
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result = """
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gpio_{}: GPIOPort.LiteX_GPIO @ {}
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type: {}
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enableIrq: {}
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{}
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""".format(name,
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generate_sysbus_registration(peripheral, skip_braces=True),
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kwargs['type'],
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'true' if kwargs['type'] != 'Type.Out' else 'false',
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ints)
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return result
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def generate_switches(csr, name, **kwargs):
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interrupt_name = '{}_interrupt'.format(name)
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result = generate_gpio_port(csr, name, **{'type': 'Type.In', 'interrupt': csr['constants'][interrupt_name], **kwargs})
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# Litex puts 4 by default into dts (litex_json2dts)
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count = int(csr['constants'].get(f'{name}_ngpio', 4))
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for i in range(0, count):
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result += """
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{name}_{i}: Miscellaneous.Button @ {periph} {i}
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-> {periph}@{i}
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""".format(name=name, periph=f"gpio_{name}", i=i)
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return result
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def generate_leds(csr, name, **kwargs):
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# Litex puts 4 by default into dts (litex_json2dts)
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count = int(csr['constants'].get(f'{name}_ngpio', 4))
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result = generate_gpio_port(csr, name,
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**{'type': 'Type.Out',
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'connections': [*range(0, count)],
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'connections_targets': [f'leds_{i}@0' for i in range(0, count)],
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**kwargs})
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for i in range(0, count):
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result += """
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{name}_{i}: Miscellaneous.LED @ {periph} {i}
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""".format(name=name, periph=f"gpio_{name}", i=i)
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return result
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def handled_peripheral(csr, name, **kwargs):
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"""
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Use this to silence warnings about unsupported peripherals, that are in reality emulated by other peripheral
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e. g. mmc, ethmac
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"""
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return ''
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peripherals_handlers = {
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'uart': {
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@ -521,7 +619,7 @@ peripherals_handlers = {
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},
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'interrupts': {
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# IRQ #100 in Renode's VexRiscv model is mapped to Machine Timer Interrupt
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'IRQ': lambda: 'cpu@100'
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'IRQ': lambda: 'cpu0@100'
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}
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},
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'ddrphy': {
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@ -559,12 +657,37 @@ peripherals_handlers = {
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'handler': generate_video_framebuffer,
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},
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'video_framebuffer_vtg': {
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'handler': lambda *args, **kwargs: "", # This is handled by generate_video_framebuffer
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}
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'handler': handled_peripheral, # This is handled by generate_video_framebuffer
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},
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'leds': {
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'handler': generate_leds,
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},
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'switches': {
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'handler': generate_switches,
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},
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'mmcm': {
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'handler': generate_peripheral,
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'model': 'Miscellaneous.LiteX_MMCM',
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'model_CSR32': 'Miscellaneous.LiteX_MMCM_CSR32',
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'ignored_constants': ['lock_timeout', 'drdy_timeout'],
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},
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'ethphy': {
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'handler': handled_peripheral # by generate_ethmac
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},
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# handled by generate_mmc
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'sdblock2mem': {
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'handler': handled_peripheral
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},
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'sdmem2block': {
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'handler': handled_peripheral
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},
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'sdcore': {
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'handler': handled_peripheral
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},
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}
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def genereate_etherbone_bridge(name, address, port):
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def generate_etherbone_bridge(name, address, port):
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# FIXME: for now the width is fixed to 0x800
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return """
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{}: EtherboneBridge @ sysbus <{}, +0x800>
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@ -572,7 +695,7 @@ def genereate_etherbone_bridge(name, address, port):
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""".format(name, hex(address), port)
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def generate_repl(csr, etherbone_peripherals, autoalign):
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def generate_repl(csr, etherbone_peripherals, autoalign, number_of_cores):
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""" Generates platform definition.
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Args:
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@ -592,7 +715,6 @@ def generate_repl(csr, etherbone_peripherals, autoalign):
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"""
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result = ""
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# RISC-V CPU in Renode requires memory region size
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# to be a multiple of 4KB - this is a known limitation
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# (not a bug) and there are no plans to handle smaller
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@ -611,16 +733,16 @@ def generate_repl(csr, etherbone_peripherals, autoalign):
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time_provider = None
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if 'clint' in csr['memories']:
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result += generate_clint(csr['memories']['clint'], csr['constants']['config_clock_frequency'])
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result += generate_clint(csr['memories']['clint'], csr['constants']['config_clock_frequency'], number_of_cores)
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time_provider = 'clint'
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if 'plic' in csr['memories']:
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result += generate_plic(csr['memories']['plic'])
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result += generate_plic(csr['memories']['plic'], number_of_cores)
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if not time_provider and 'cpu' in csr['csr_bases']:
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time_provider = 'cpu_timer'
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result += generate_cpu(csr, time_provider)
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result += generate_cpu(csr, time_provider, number_of_cores)
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for name, address in csr['csr_bases'].items():
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if name not in peripherals_handlers:
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@ -631,7 +753,7 @@ def generate_repl(csr, etherbone_peripherals, autoalign):
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if name in etherbone_peripherals:
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# generate an etherbone bridge for the peripheral
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port = etherbone_peripherals[name]
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result += genereate_etherbone_bridge(name, address, port)
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result += generate_etherbone_bridge(name, address, port)
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pass
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else:
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# generate an actual model of the peripheral
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@ -674,6 +796,8 @@ def filter_memory_regions(raw_regions, alignment=None, autoalign=[]):
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size_mismatch = r['size'] % alignment
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address_mismatch = r['base'] % alignment
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def print_autoalign_hint():
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print('Hint: use "--auto-align {}" to force automatic alignement of the region'.format(r['name']))
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if address_mismatch != 0:
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if r['name'] in autoalign:
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r['original_address'] = r['base']
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@ -681,6 +805,7 @@ def filter_memory_regions(raw_regions, alignment=None, autoalign=[]):
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print('Re-aligning `{}` memory region base address from {} to {} due to limitations in Renode'.format(r['name'], hex(r['original_address']), hex(r['base'])))
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else:
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print('Error: `{}` memory region base address ({}) is not aligned to {}. This configuration cannot be currently simulated in Renode'.format(r['name'], hex(r['size']), hex(alignment)))
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print_autoalign_hint()
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sys.exit(1)
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if size_mismatch != 0:
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@ -690,6 +815,7 @@ def filter_memory_regions(raw_regions, alignment=None, autoalign=[]):
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print('Extending `{}` memory region size from {} to {} due to limitations in Renode'.format(r['name'], hex(r['original_size']), hex(r['size'])))
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else:
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print('Error: `{}` memory region size ({}) is not aligned to {}. This configuration cannot be currently simulated in Renode'.format(r['name'], hex(r['size']), hex(alignment)))
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print_autoalign_hint()
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sys.exit(1)
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if r['size'] == 0:
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@ -730,7 +856,7 @@ def find_memory_region(memory_regions, address):
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return None
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def generate_resc(csr, args, flash_binaries={}, tftp_binaries={}):
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def generate_resc(csr, number_of_cores, args, flash_binaries={}, tftp_binaries={}):
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""" Generates platform definition.
|
||||
|
||||
Args:
|
||||
|
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@ -756,14 +882,15 @@ showAnalyzer sysbus.uart
|
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showAnalyzer sysbus.uart Antmicro.Renode.Analyzers.LoggingUartAnalyzer
|
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""".format(cpu_type, args.repl)
|
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|
||||
rom_base = csr['memories']['rom']['base'] if 'rom' in csr['memories'] else None
|
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if rom_base is not None and args.bios_binary:
|
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opensbi_base = csr['memories']['opensbi']['base'] if 'opensbi' in csr['memories'] else None
|
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if opensbi_base is not None and args.bios_binary:
|
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# load LiteX BIOS to ROM
|
||||
result += """
|
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sysbus LoadBinary @{} {}
|
||||
cpu PC {}
|
||||
""".format(args.bios_binary, rom_base, rom_base)
|
||||
""".format(args.bios_binary, hex(opensbi_base))
|
||||
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||||
for cpu_id in range(0, number_of_cores):
|
||||
result += f"cpu{cpu_id} PC {hex(opensbi_base)}\n"
|
||||
|
||||
if args.tftp_ip:
|
||||
result += """
|
||||
|
|
@ -792,16 +919,16 @@ connector Connect ethmac switch
|
|||
connector Connect host.tap switch
|
||||
""".format(args.configure_network)
|
||||
elif flash_binaries:
|
||||
if 'flash_boot_address' not in csr['constants']:
|
||||
if 'spiflash' not in csr['memories']:
|
||||
print('Warning! There is no flash memory to load binaries to')
|
||||
else:
|
||||
# load binaries to spiflash to boot from there
|
||||
|
||||
for offset in flash_binaries:
|
||||
path = flash_binaries[offset]
|
||||
flash_boot_address = int(csr['constants']['flash_boot_address'], 0) + offset
|
||||
flash_boot_address = int(csr['memories']['spiflash']['base']) + offset
|
||||
|
||||
firmware_data = open(path, 'rb').read()
|
||||
firmware_data = open(os.path.expanduser(path), 'rb').read()
|
||||
crc32 = zlib.crc32(firmware_data)
|
||||
|
||||
result += 'sysbus WriteDoubleWord {} {}\n'.format(hex(flash_boot_address), hex(len(firmware_data)))
|
||||
|
|
@ -950,8 +1077,10 @@ def main():
|
|||
|
||||
etherbone_peripherals = check_etherbone_peripherals(args.etherbone_peripherals)
|
||||
|
||||
number_of_cores = get_cpu_count(csr)
|
||||
|
||||
if args.repl:
|
||||
print_or_save(args.repl, generate_repl(csr, etherbone_peripherals, args.autoalign_memor_regions))
|
||||
print_or_save(args.repl, generate_repl(csr, etherbone_peripherals, args.autoalign_memor_regions, number_of_cores))
|
||||
|
||||
if args.resc:
|
||||
if not args.repl:
|
||||
|
|
@ -961,7 +1090,7 @@ def main():
|
|||
flash_binaries = parse_flash_binaries(csr, args)
|
||||
tftp_binaries = check_tftp_binaries(args)
|
||||
|
||||
print_or_save(args.resc, generate_resc(csr, args,
|
||||
print_or_save(args.resc, generate_resc(csr, number_of_cores, args,
|
||||
flash_binaries,
|
||||
tftp_binaries))
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue